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    • 3. 发明授权
    • Data signal improvement using signal peak detectors in a receiver
    • 在接收机中使用信号峰值检测器进行数据信号改进
    • US09020075B2
    • 2015-04-28
    • US12711781
    • 2010-02-24
    • Osamu KobayashiGyo Un Choi
    • Osamu KobayashiGyo Un Choi
    • H03K9/00H04L25/03
    • H04L25/03006
    • Methods and systems are described for improving a data at a receiver using one or more signal peak detectors. A signal is received having an initial signal level from the transmitter, the signal having a long bit and a short bit. The initial signal voltage of the signal is measured using a signal peak detector. A pre-emphasis value is determined using the signal voltage and is communicated to the transmitter, causing the transmitter to transmit the signal using an adjusted signal level. A second signal voltage of the initial signal is measured using a second signal peak detector, the second signal voltage being used to determine the pre-emphasis value. In another embodiment, a state machine having data relating to appropriate pre-emphasis is used in determining the pre-emphasis value. In another embodiment, one peak detector is used to measure the long bit and another peak detector is used to measure the short bit. In another embodiment, the signal does not have associated link training data.
    • 描述了用于使用一个或多个信号峰值检测器来改善接收机处的数据的方法和系统。 接收到具有来自发射机的初始信号电平的信号,该信号具有长位和短位。 使用信号峰值检测器来测量信号的初始信号电压。 使用信号电压确定预加重值,并将其传送到发射机,使得发射机使用调整的信号电平来发射信号。 使用第二信号峰值检测器测量初始信号的第二信号电压,第二信号电压用于确定预加重值。 在另一个实施例中,在确定预加重值时使用具有与适当预加重相关的数据的状态机。 在另一个实施例中,使用一个峰值检测器来测量长位,另一个峰值检测器用于测量短位。 在另一个实施例中,该信号没有相关联的链路训练数据。
    • 7. 发明授权
    • Data link configuration by a receiver in the absence of link training data
    • 数据链路配置由接收者在没有链路训练数据的情况下
    • US08582452B2
    • 2013-11-12
    • US12711569
    • 2010-02-24
    • Osamu Kobayashi
    • Osamu Kobayashi
    • H04L12/26H04J3/06H04J3/16
    • H04N21/44231G09G5/006G09G5/008G09G2370/10H04N21/4122H04N21/43632
    • A receiver is enabled to perform self-configuration of the main data link to receive and display video data. A video data signal is received through a data link having multiple channels or lanes at a specific bit rate. No link configuration data normally associated with the video signal is received. It is then determined which one or more of the channels of the data link are active in transmitting the data signal. A symbol pattern in the data signal is then identified. The symbol rate of the data signal is then synchronized with the local clock frequency. The local clock frequency is set to correspond to the actual bit rate of the data signal, thereby creating a signal-based clock frequency. This local clock frequency is set using only the data signal since no link configuration data associated with the signal is received. In this manner, the receiver configures or trains the link itself using only the video data signal and therefore, the receiver may be described as self-sufficient.
    • 接收机能够执行主数据链路的自配置以接收和显示视频数据。 通过具有特定比特率的多个信道或通道的数据链路接收视频数据信号。 不接收通常与视频信号相关联的链路配置数据。 然后确定在发送数据信号时数据链路的哪一个或多个信道是有效的。 然后识别数据信号中的符号图案。 然后数据信号的符号速率与本地时钟频率同步。 本地时钟频率被设置为对应于数据信号的实际比特率,从而产生基于信号的时钟频率。 该本地时钟频率仅由数据信号设置,因为没有接收到与该信号相关联的链路配置数据。 以这种方式,接收机仅使用视频数据信号来配置或训练链路本身,因此接收机可以被描述为自足的。
    • 10. 发明授权
    • Flat panel display driver method and system
    • 平板显示驱动方法及系统
    • US08429440B2
    • 2013-04-23
    • US12760467
    • 2010-04-14
    • Osamu Kobayashi
    • Osamu Kobayashi
    • G06F1/04H04N5/44
    • G06F1/04G09G5/006G09G2330/021G09G2370/10G09G2370/14
    • Methods and systems are described for enabling display system data transmission during use. An integrated circuit package includes input interface circuitry configured to receive an audio-video data stream having a video signal and timing information and timing extraction circuitry that can identify blanking patterns for the video signal. The package includes input processing circuitry for receiving audio-video signal and converting the audio-video data stream input into a low voltage differential signal (LVDS). The package includes a timing controller having timing extraction circuitry, a set of symbol buffers, a scheduler, and timing control circuitry. All configured to implement LVDS data transfer and in some implementation enable point to point data transfer from data buffers to associated column drivers.
    • 描述了在使用期间使显示系统数据传输的方法和系统。 集成电路封装包括输入接口电路,其被配置为接收具有视频信号和定时信息的音频 - 视频数据流以及可识别视频信号的消​​隐模式的定时提取电路。 该包装包括用于接收音频 - 视频信号并将音频 - 视频数据流输入转换成低电压差分信号(LVDS)的输入处理电路。 该封装包括具有定时提取电路,一组符号缓冲器,调度器和定时控制电路的定时控制器。 所有这些都配置为实现LVDS数据传输,并且在某些实现中,使得能够从数据缓冲区到相关列驱动器进行点对点数据传输。