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1. 发明授权

US07035142B2 Non volatile memory device including a predetermined number of sectors 有权
标题翻译：包括预定数量的扇区的非易失性存储器件
公开(公告)号：US07035142B2
公开(公告)日：2006-04-25
申请号：US10748696
申请日：2003-12-30
申请人： Osama Khouri , Roberto Ravasio , Rino Micheloni , Giovanni Campardo
发明人： Osama Khouri , Roberto Ravasio , Rino Micheloni , Giovanni Campardo
IPC分类号： G11C16/06
CPC分类号： G11C29/76
摘要： The device includes a circuit for sector remapping having a CAM (Content Addressable Memory) unit, associated to and in data communication with a multiplexer unit. The CAM unit detects that a sector is defective, it provides the pre-programmed address of a replacing sector and it activates the multiplexer which performs the replacement. The defective sectors and the corresponding locations of the address map are therefore advantageously positioned to the rear to the addressing area. The addressing area is consequently continuous, thus allowing the information to be easily stored and retrieved.
摘要翻译：该设备包括用于扇区重新映射的电路，其具有与多路复用器单元相关联并且与多路复用器单元进行数据通信的CAM（内容可寻址存储器）单元。 CAM单元检测到扇区有故障，它提供替换扇区的预编程地址，并激活执行替换的多路复用器。因此，有缺陷的扇区和地址图的相应位置有利地位于寻址区的后方。因此，寻址区域是连续的，从而可以容易地存储和检索信息。

2. 发明授权

US06249112B1 Voltage regulating circuit for a capacitive load 有权
标题翻译：用于容性负载的电压调节电路
公开(公告)号：US06249112B1
公开(公告)日：2001-06-19
申请号：US09608445
申请日：2000-06-29
申请人： Osama Khouri , Rino Micheloni , Ilaria Motta , Guido Torelli
发明人： Osama Khouri , Rino Micheloni , Ilaria Motta , Guido Torelli
IPC分类号： G05F140
CPC分类号： G05F3/242
摘要： Presented is a voltage regulating circuit for a capacitive load, which is connected between first and second terminals of a supply voltage generator. The regulating circuit has an input terminal and an output terminal, and includes an operational amplifier having an inverting input terminal connected to the input terminal of the regulating circuit and a non-inverting input terminal connected to an intermediate node of a voltage divider. The voltage divider is connected between an output node, which is connected to the output terminal of the regulating circuit, and the second terminal of the supply voltage generator. The operational amplifier has an output terminal connected, for driving a first field-effect transistor, between the output node and the first terminal of the supply voltage generator. The output terminal of the operational amplifier is also connected to the output node through a compensation network. The voltage regulating circuit also includes a second field-effect transistor connected between the output node and the second terminal of the supply voltage generator, which has its gate terminal connected to a constant voltage generating circuit means.
摘要翻译：提出了一种用于容性负载的电压调节电路，其连接在电源电压发生器的第一和第二端子之间。调节电路具有输入端子和输出端子，并且包括具有连接到调节电路的输入端子的反相输入端子和连接到分压器的中间节点的非反相输入端子的运算放大器。分压器连接在与调节电路的输出端子连接的输出节点和电源电压发生器的第二端子之间。运算放大器在输出节点和电源电压发生器的第一端之间连接有用于驱动第一场效应晶体管的输出端子。运算放大器的输出端也通过补偿网络连接到输出节点。电压调节电路还包括连接在电源电压发生器的输出节点和第二端子之间的第二场效应晶体管，其栅极端子连接到恒压产生电路装置。

3. 发明授权

US06650173B1 Programmable voltage generator 有权
标题翻译：可编程电压发生器
公开(公告)号：US06650173B1
公开(公告)日：2003-11-18
申请号：US09714852
申请日：2000-11-15
申请人： Osama Khouri , Rino Micheloni , Andrea Sacco , Guido Torelli
发明人： Osama Khouri , Rino Micheloni , Andrea Sacco , Guido Torelli
IPC分类号： G05F110
CPC分类号： G11C29/021 , G11C5/147 , G11C11/56 , G11C16/30 , G11C29/028 , G11C2029/5004
摘要： The voltage generator comprises a negative feedback loop including a programmable voltage divider having a feedback node. The voltage divider comprises a programmable resistor disposed between the output of the voltage generator and the feedback node and having variable resistance. The programmable resistor includes a fixed resistor and a plurality of additional resistors arranged in series with each other and defining a plurality of intermediate nodes. The additional resistors may be selectively connected by means of switches disposed between the output of the voltage generator and a respective intermediate node so as to define an output voltage V0 programmable on the basis of command signals supplied to the switches.
摘要翻译：电压发生器包括负反馈回路，其包括具有反馈节点的可编程分压器。分压器包括设置在电压发生器的输出端和反馈节点之间并具有可变电阻的可编程电阻器。可编程电阻器包括固定电阻器和彼此串联布置并且限定多个中间节点的多个附加电阻器。附加电阻器可以通过设置在电压发生器的输出端和各个中间节点之间的开关选择性地连接，以便根据提供给开关的命令信号来定义可编程的输出电压V0。

4. 发明授权

US06373780B1 Single supply voltage nonvolatile memory device with row decoding 有权
标题翻译：单电源电压非易失性存储器件，具有行解码功能
公开(公告)号：US06373780B1
公开(公告)日：2002-04-16
申请号：US09627273
申请日：2000-07-28
申请人： Rino Micheloni , Osama Khouri , Andrea Sacco , Massimiliano Picca
发明人： Rino Micheloni , Osama Khouri , Andrea Sacco , Massimiliano Picca
IPC分类号： G11C800
CPC分类号： G11C5/145 , G11C5/14 , G11C8/10
摘要： The memory device comprises a memory array having an organization of the type comprising global word lines and local word lines, a global row decoder addressing the global word lines, a local row decoder addressing the local word lines, a global power supply stage supplying the global row decoder, and a local power supply stage supplying the local row decoder.
摘要翻译：存储器件包括具有包括全局字线和本地字线的组织的存储器阵列，寻址全局字线的全局行解码器，寻址本地字线的本地行解码器，提供全局字线的全局电源级行解码器，以及供应本地行解码器的本地电源级。

5. 发明授权

US06788579B2 Method for programming nonvolatile memory cells with program and verify algorithm using a staircase voltage with varying step amplitude 有权
标题翻译：使用程序和验证算法编程非易失性存储单元的方法，使用具有不同步长幅度的阶梯电压
公开(公告)号：US06788579B2
公开(公告)日：2004-09-07
申请号：US10119523
申请日：2002-04-09
申请人： Stefano Gregori , Rino Micheloni , Andrea Pierin , Osama Khouri , Guido Torelli
发明人： Stefano Gregori , Rino Micheloni , Andrea Pierin , Osama Khouri , Guido Torelli
IPC分类号： G11C1604
CPC分类号： G11C11/5628 , G11C16/12
摘要： A method for programming a nonvolatile memory cell envisages applying in succession, to the gate terminal of the memory cell, a first and a second programming pulse trains with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next in the first programming pulse train is greater than the amplitude increment between one pulse and the next in the second programming pulse train. The programming method envisages applying, to the gate terminal of the memory cell and before the first programming pulse train, a third programming pulse train with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next may be less than the amplitude increment in the first programming pulse train and substantially equal to the amplitude increment in the second programming pulse train, or else may be greater than the amplitude increment in the first programming pulse train.
摘要翻译：用于编程非易失性存储器单元的方法设想连续地应用到存储器单元的栅极端，第一和第二编程脉冲串，其阶梯形式的脉冲幅度增加，其中在一个脉冲和下一个脉冲之间的振幅增量第一编程脉冲序列大于第二编程脉冲串中的一个脉冲和下一个脉冲之间的振幅增量。编程方法设想在存储器单元的栅极端子和第一编程脉冲串之前施加具有阶梯式脉冲幅度增加的第三编程脉冲串，其中，一个脉冲与下一个脉冲之间的振幅增量可能小于第一编程脉冲序列中的振幅增量基本上等于第二编程脉冲串中的幅度增量，或者可以大于第一编程脉冲序列中的振幅增量。

6. 发明授权

US06259632B1 Capacitive compensation circuit for the regulation of the word line reading voltage in non-volatile memories 有权
标题翻译：用于调节非易失性存储器中字线读取电压的电容补偿电路
公开(公告)号：US06259632B1
公开(公告)日：2001-07-10
申请号：US09491475
申请日：2000-01-19
申请人： Osama Khouri , Rino Micheloni , Ilaria Motta , Andrea Sacco , Guido Torelli
发明人： Osama Khouri , Rino Micheloni , Ilaria Motta , Andrea Sacco , Guido Torelli
IPC分类号： G11C1606
CPC分类号： G11C11/5621 , G11C8/14 , G11C16/08 , G11C16/30
摘要： Circuit for the regulation of the word line voltage in a memory, including a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more word lines of the memory when said one or more word lines are being selected, and charge accumulation means that are selectively connectable with the output of the voltage regulator and suitable to accumulate a compensation charge for a voltage drop that takes place on said regulated voltage upon the selection of said one or more word lines of the memory.
摘要翻译：用于调节存储器中的字线电压的电路，包括适于在选择所述一个或多个字线时产生要提供给存储器的一个或多个字线的输出调节电压的电压调节器，以及电荷累积意味着可以选择性地与电压调节器的输出端连接，并且适合于在选择存储器的所述一个或多个字线时，对在所述调节电压上发生的电压降累积补偿电荷。

7. 发明授权

US07777466B2 Voltage regulator or non-volatile memories implemented with low-voltage transistors 有权
标题翻译：用低压晶体管实现的稳压器或非易失性存储器
公开(公告)号：US07777466B2
公开(公告)日：2010-08-17
申请号：US11844470
申请日：2007-08-24
申请人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Giovanni Campardo , Rino Micheloni
发明人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Giovanni Campardo , Rino Micheloni
IPC分类号： G05F1/40
CPC分类号： G11C5/147 , G05F1/565 , G11C16/30
摘要： A voltage regulator integrated in a chip of semiconductor material is provided. The regulator has a first input terminal for receiving a first voltage and an output terminal for providing a regulated voltage being obtained from the first voltage, the regulator including: a differential amplifier for receiving a comparison voltage and a feedback signal being a function of the regulated voltage, and for proving a regulation signal according to a comparison between the comparison voltage and the feedback signal, the differential amplifier having a first supply terminal being coupled with a reference terminal for receiving a reference voltage and a second supply terminal, a regulation transistor having a control terminal for receiving the regulation signal, and a conduction first terminal and a conduction second terminal being coupled through loading means between the reference terminal and the first input terminal of the regulator, the second terminal of the regulation transistor being coupled with the output terminal of the regulator, wherein the second supply terminal of the differential amplifier is coupled with a second input terminal of the regulator for receiving a second voltage being lower than the first voltage in absolute value, and wherein the regulator further includes a set of auxiliary transistors being connected in series between the second terminal of the regulation transistor and the output terminal of the regulator, and control means for controlling the auxiliary transistors according to the regulated voltage.
摘要翻译：提供集成在半导体材料芯片中的电压调节器。所述调节器具有用于接收第一电压的第一输入端子和用于提供从所述第一电压获得的调节电压的输出端子，所述调节器包括：用于接收比较电压的差分放大器和作为所述第一电压的函数的反馈信号电压，并且为了根据比较电压和反馈信号之间的比较来证明调节信号，差分放大器具有与用于接收参考电压的参考端子耦合的第一电源端子和第二电源端子，调节晶体管具有用于接收所述调节信号的控制端子，以及通过所述参考端子和所述调节器的所述第一输入端子之间的负载装置耦合的导通第一端子和导通第二端子，所述调节晶体管的所述第二端子与所述输出端子的调节器，其中第二电源差分放大器的nal与调节器的第二输入端耦合，用于接收低于绝对值中的第一电压的第二电压，并且其中调节器还包括一组辅助晶体管，串联连接在第二端调节器的调节晶体管和输出端子，以及用于根据调节电压控制辅助晶体管的控制装置。

8. 发明授权

US07027317B2 Semiconductor memory with embedded DRAM 失效
标题翻译：具有嵌入式DRAM的半导体存储器
公开(公告)号：US07027317B2
公开(公告)日：2006-04-11
申请号：US10720013
申请日：2003-11-20
申请人： Giovanni Campardo , Rino Micheloni
发明人： Giovanni Campardo , Rino Micheloni
IPC分类号： G11C11/24 , G11C14/00
CPC分类号： G11C11/005
摘要： A semiconductor memory comprises a plurality of memory cells, for example Flash memory cells, arranged in a plurality of lines, and a plurality of memory cell access signal lines, each one associated with at least one respective line of memory cells, for accessing the memory cells of the at least one respective line of memory cells; each signal line has a capacitance intrinsically associated therewith. A plurality of volatile memory cells is provided, each having a capacitive storage element. Each volatile memory cell is associated with a respective signal line, and the respective capacitive storage element formed by the capacitance intrinsically associated with the respective signal lines. In particular, the parasitic capacitances associated with bit lines of a matrix of memory cells can be exploited as capacitive storage elements.
摘要翻译：半导体存储器包括多个存储器单元，例如布置在多个行中的闪存单元，以及多个存储单元存取信号线，每个存储单元接入信号线与至少一个相应行的存储单元相关联，用于访问存储器存储单元的至少一个相应行的单元; 每个信号线具有与其固有相关的电容。提供了多个易失性存储单元，每个易失性存储单元具有电容存储元件。每个易失性存储器单元与相应的信号线相关联，并且由与各个信号线固有相关联的电容形成的相应电容存储元件。特别地，与存储器单元的矩阵的位线相关联的寄生电容可以被用作电容性存储元件。

9. 发明授权

US06327184B1 Read circuit for a nonvolatile memory 有权
标题翻译：读取非易失性存储器的电路
公开(公告)号：US06327184B1
公开(公告)日：2001-12-04
申请号：US09621019
申请日：2000-07-21
申请人： Rino Micheloni , Giovanni Campardo , Luca Crippa
发明人： Rino Micheloni , Giovanni Campardo , Luca Crippa
IPC分类号： G11C1606
CPC分类号： G11C16/28
摘要： The read circuit comprises an array branch having an input array node connected, via an array bit line, to an array cell; a reference branch having an input reference node connected, via a reference bit line, to a reference cell; a current-to-voltage converter connected to an output array node of the array branch and to an output reference node of the reference branch to supply on the output array node and the output reference node the respective electric potentials correlated to the currents flowing in the array memory cell and, respectively, in the reference memory cell; and a comparator connected at input to the output array node and output reference node and supplying as output a signal indicative of the contents stored in the array memory cell; and an array decoupling stage arranged between the input array node and the output array node to decouple the electric potentials of the input and output array nodes from one another.
摘要翻译：读取电路包括具有通过阵列位线连接到阵列单元的输入阵列节点的阵列分支; 参考分支，其具有通过参考位线连接到参考单元的输入参考节点; 连接到阵列分支的输出阵列节点和参考分支的输出参考节点的电流 - 电压转换器，以在输出阵列节点和输出参考节点上提供与在阵列存储单元，分别在参考存储单元中; 以及比较器，其输入端连接到所述输出阵列节点和输出参考节点，并且作为输出提供指示存储在所述阵列存储单元中的内容的信号; 以及布置在输入阵列节点和输出阵列节点之间的阵列解耦级，以将输入和输出阵列节点的电位彼此去耦。

10. 发明授权

US06237104B1 Method and a related circuit for adjusting the duration of a synchronization signal ATD for timing the access to a non-volatile memory 有权
标题翻译：方法和相关电路，用于调整同步信号ATD的持续时间，用于定时访问非易失性存储器
公开(公告)号：US06237104B1
公开(公告)日：2001-05-22
申请号：US09222070
申请日：1998-12-29
申请人： Rino Micheloni , Giovanni Campardo , Stefano Commodaro , Guido Lomazzi
发明人： Rino Micheloni , Giovanni Campardo , Stefano Commodaro , Guido Lomazzi
IPC分类号： G06F1200
CPC分类号： G11C8/18 , G11C16/32
摘要： A method and related circuit for adjusting the duration of a pulse synchronization signal for the reading phase of memory cells in electronic memory devices which are integrated on semiconductors are discussed. The pulse synchronization signal is produced by a pulse generator when it detects a logical state commutation on at least one input terminal of a plurality of addressing input terminals of the memory cells. The method produces a logical sum between the signal produced by the generator and a pulse signal having a predetermined duration. The logical sum is used to start up the reading phase.
摘要翻译：讨论了用于调整集成在半导体上的电子存储器件中的存储器单元的读取阶段的脉冲同步信号的持续时间的方法和相关电路。当脉冲同步信号检测到存储器单元的多个寻址输入端的至少一个输入端上的逻辑状态换向时，脉冲同步信号由脉冲发生器产生。该方法产生由发生器产生的信号与具有预定持续时间的脉冲信号之间的逻辑和。逻辑和用于启动读取阶段。

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