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1. 发明申请

US20170017492A1 APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS 审中-公开
公开(公告)号：US20170017492A1
公开(公告)日：2017-01-19
申请号：US15282082
申请日：2016-09-30
申请人： Oren Ben-Kiki , ILAN PARDO , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
发明人： Oren Ben-Kiki , ILAN PARDO , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
IPC分类号： G06F9/38 , G06F12/0875 , G06F9/30
CPC分类号： G06F9/3802 , G06F9/3004 , G06F9/30043 , G06F9/30076 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F9/384 , G06F9/3877 , G06F9/3879 , G06F9/3881 , G06F9/54 , G06F11/0721 , G06F11/0724 , G06F11/0772 , G06F12/0875 , G06F2212/452
摘要： An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why the commend could not be executed; execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands, the accelerator invocation instruction to store command data specifying the command within the command register; one or more accelerators to read the command data from the command register and responsively attempt to execute the command identified by the command data, wherein if the one or more accelerators successfully execute the command, the one or more accelerators are to store result data comprising the results of the command in the result register; and if the one or more accelerators cannot successfully execute the command, the one or more accelerators are to store result data indicating a reason why the command cannot be executed, wherein the execution logic is to temporarily halt execution until the accelerator completes execution or is interrupted, wherein the accelerator includes logic to store its state if interrupted so that it can continue execution at a later time.

2. 发明申请

US20170017491A1 APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS 审中-公开
标题翻译：低速延迟加速器的装置和方法
公开(公告)号：US20170017491A1
公开(公告)日：2017-01-19
申请号：US15281944
申请日：2016-09-30
申请人： Oren Ben-Kiki , ILAN PARDO , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
发明人： Oren Ben-Kiki , ILAN PARDO , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
IPC分类号： G06F9/38 , G06F12/0875 , G06F9/30
CPC分类号： G06F9/3802 , G06F9/3004 , G06F9/30043 , G06F9/30076 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F9/384 , G06F9/3877 , G06F9/3879 , G06F9/3881 , G06F9/54 , G06F11/0721 , G06F11/0724 , G06F11/0772 , G06F12/0875 , G06F2212/452
摘要： An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why the commend could not be executed; execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands, the accelerator invocation instruction to store command data specifying the command within the command register; one or more accelerators to read the command data from the command register and responsively attempt to execute the command identified by the command data, wherein if the one or more accelerators successfully execute the command, the one or more accelerators are to store result data comprising the results of the command in the result register; and if the one or more accelerators cannot successfully execute the command, the one or more accelerators are to store result data indicating a reason why the command cannot be executed, wherein the execution logic is to temporarily halt execution until the accelerator completes execution or is interrupted, wherein the accelerator includes logic to store its state if interrupted so that it can continue execution at a later time.
摘要翻译：描述了一种用于提供加速器的低延迟调用的装置和方法。例如，根据一个实施例的处理器包括：命令寄存器，用于存储标识要执行的命令的命令数据; 用于存储命令结果的结果寄存器或指示不能执行推荐的原因的数据; 执行逻辑以执行包括用于调用一个或多个加速器命令的加速器调用指令的多个指令，所述加速器调用指令将指定所述命令的命令数据存储在所述命令寄存器内; 一个或多个加速器，用于从命令寄存器读取命令数据，并且响应地尝试执行由命令数据识别的命令，其中如果一个或多个加速器成功执行命令，则一个或多个加速器将存储包括结果寄存器中的命令结果; 并且如果一个或多个加速器不能成功地执行命令，则一个或多个加速器将存储指示不能执行该命令的原因的结果数据，其中执行逻辑将暂停执行，直到加速器完成执行或被中断其中所述加速器包括用于存储其状态的逻辑，如果被中断，使得其可以在稍后的时间继续执行。

3. 发明申请

US20140189332A1 APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS 有权
标题翻译：低速延迟加速器的装置和方法
公开(公告)号：US20140189332A1
公开(公告)日：2014-07-03
申请号：US13729915
申请日：2012-12-28
申请人： Oren Ben-Kiki , Ilan Pardo , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
发明人： Oren Ben-Kiki , Ilan Pardo , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/3004 , G06F9/30043 , G06F9/30076 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F9/384 , G06F9/3877 , G06F9/3879 , G06F9/3881 , G06F9/54 , G06F11/0721 , G06F11/0724 , G06F11/0772 , G06F12/0875 , G06F2212/452
摘要： An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why the command could not be executed; execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands; and one or more accelerators to read the command data from the command register and responsively attempt to execute the command identified by the command data.
摘要翻译：描述了一种用于提供加速器的低延迟调用的装置和方法。例如，根据一个实施例的处理器包括：命令寄存器，用于存储标识要执行的命令的命令数据; 用于存储命令结果的结果寄存器或表示无法执行命令的原因的数据; 执行逻辑以执行包括调用一个或多个加速器命令的加速器调用指令的多个指令; 以及一个或多个加速器，用于从命令寄存器读取命令数据，并且响应地尝试执行由命令数据识别的命令。

4. 发明申请

US20160246597A1 APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS 审中-公开
标题翻译：低速延迟加速器的装置和方法
公开(公告)号：US20160246597A1
公开(公告)日：2016-08-25
申请号：US15145748
申请日：2016-05-03
申请人： Oren Ben-Kiki , llan Pardo , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
发明人： Oren Ben-Kiki , llan Pardo , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/3004 , G06F9/30043 , G06F9/30076 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F9/384 , G06F9/3877 , G06F9/3879 , G06F9/3881 , G06F9/54 , G06F11/0721 , G06F11/0724 , G06F11/0772 , G06F12/0875 , G06F2212/452
摘要： An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why the commend could not be executed; execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands, the accelerator invocation instruction to store command data specifying the command within the command register; one or more accelerators to read the command data from the command register and responsively attempt to execute the command identified by the command data, wherein if the one or more accelerators successfully execute the command, the one or more accelerators are to store result data comprising the results of the command in the result register; and if the one or more accelerators cannot successfully execute the command, the one or more accelerators are to store result data indicating a reason why the command cannot be executed, wherein the execution logic is to temporarily halt execution until the accelerator completes execution or is interrupted, wherein the accelerator includes logic to store its state if interrupted so that it can continue execution at a later time.
摘要翻译：描述了一种用于提供加速器的低延迟调用的装置和方法。例如，根据一个实施例的处理器包括：命令寄存器，用于存储标识要执行的命令的命令数据; 用于存储命令结果的结果寄存器或指示不能执行推荐的原因的数据; 执行逻辑以执行包括用于调用一个或多个加速器命令的加速器调用指令的多个指令，所述加速器调用指令将指定所述命令的命令数据存储在所述命令寄存器内; 一个或多个加速器，用于从命令寄存器读取命令数据并响应于尝试执行由命令数据识别的命令，其中如果一个或多个加速器成功地执行命令，则一个或多个加速器将存储包括结果寄存器中的命令结果; 并且如果一个或多个加速器不能成功地执行命令，则一个或多个加速器将存储指示不能执行该命令的原因的结果数据，其中执行逻辑将暂停执行，直到加速器完成执行或被中断其中所述加速器包括用于存储其状态的逻辑，如果被中断，使得其可以在稍后的时间继续执行。

5. 发明授权

US09053025B2 Apparatus and method for fast failure handling of instructions 有权
标题翻译：快速故障处理指令的装置和方法
公开(公告)号：US09053025B2
公开(公告)日：2015-06-09
申请号：US13729931
申请日：2012-12-28
申请人： Oren Ben-Kiki , Ilan Pardo , Robert Valentine
发明人： Oren Ben-Kiki , Ilan Pardo , Robert Valentine
IPC分类号： G06F11/00 , G06F11/07 , G06F11/14 , G06F9/38
CPC分类号： G06F11/0793 , G06F9/3842 , G06F11/0721 , G06F11/0724 , G06F11/0751 , G06F11/076 , G06F11/0772 , G06F11/1438
摘要： A processor is described comprising: instruction failure logic to perform a plurality of operations in response to a detected instruction execution failure, the instruction failure logic to be used for instructions which have complex failure modes and which are expected to have a failure frequency above a threshold, wherein the operations include: detecting an instruction execution failure and determining a reason for the failure; storing failure data in a destination register to indicate the failure and to specify details associated with the failure; and allowing application program code to read the failure data and responsively take one or more actions responsive to the failure, wherein the instruction failure logic performs its operations without invocation of an exception handler or switching to a low level domain on a system which employs hierarchical protection domains.
摘要翻译：描述了一种处理器，包括：响应于检测到的指令执行失败执行多个操作的指令失败逻辑，用于具有复杂故障模式并且预期具有高于阈值的故障频率的指令的指令故障逻辑其中，所述操作包括：检测指令执行失败并确定所述故障的原因; 将故障数据存储在目的地寄存器中以指示故障并指定与故障相关的细节; 并且允许应用程序代码读取故障数据并且响应于故障响应地采取一个或多个动作，其中指令失败逻辑执行其操作而不调用异常处理程序或切换到采用分级保护的系统上的低级域域名

6. 发明申请

US20140189426A1 APPARATUS AND METHOD FOR FAST FAILURE HANDLING OF INSTRUCTIONS 有权
标题翻译：快速故障处理指令的装置和方法
公开(公告)号：US20140189426A1
公开(公告)日：2014-07-03
申请号：US13729931
申请日：2012-12-28
申请人： Oren Ben-Kiki , Ilan Pardo , Robert Valentine
发明人： Oren Ben-Kiki , Ilan Pardo , Robert Valentine
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F9/3842 , G06F11/0721 , G06F11/0724 , G06F11/0751 , G06F11/076 , G06F11/0772 , G06F11/1438
摘要： A processor is described comprising: instruction failure logic to perform a plurality of operations in response to a detected instruction execution failure, the instruction failure logic to be used for instructions which have complex failure modes and which are expected to have a failure frequency above a threshold, wherein the operations include: detecting an instruction execution failure and determining a reason for the failure; storing failure data in a destination register to indicate the failure and to specify details associated with the failure; and allowing application program code to read the failure data and responsively take one or more actions responsive to the failure, wherein the instruction failure logic performs its operations without invocation of an exception handler or switching to a low level domain on a system which employs hierarchical protection domains.
摘要翻译：描述了一种处理器，包括：响应于检测到的指令执行失败执行多个操作的指令失败逻辑，用于具有复杂故障模式并且预期具有高于阈值的故障频率的指令的指令故障逻辑其中，所述操作包括：检测指令执行失败并确定所述故障的原因; 将故障数据存储在目的地寄存器中以指示故障并指定与故障相关的细节; 并且允许应用程序代码读取故障数据并且响应于故障响应地采取一个或多个动作，其中指令失败逻辑执行其操作而不调用异常处理程序或切换到采用分级保护的系统上的低级域域名

7. 发明授权

US10474463B2 Apparatus and method for down conversion of data types 有权
公开(公告)号：US10474463B2
公开(公告)日：2019-11-12
申请号：US13997006
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Tal Uliel , Jesus Corbal , Zeev Sperber , Amit Gradstein
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Tal Uliel , Jesus Corbal , Zeev Sperber , Amit Gradstein
IPC分类号： G06F9/30
摘要： An apparatus and method are described for down-converting from a source operand to a destination operand with masking. For example, a method according to one embodiment includes the following operations: reading a source operand value to be down-converted from a first value to a down-converted value and stored in a destination location; reading each mask register bit stored in a mask register, the mask register bit(s) indicating whether to perform a masking operation or a conversion operation on the source operand value; if the mask register bit(s) indicates that a masking operation is to be performed, then performing a specified masking operation and storing the results of the masking operation in the destination location; and if the mask register bit indicates that a masking operation is not to be performed, then down-converting the source operand value and storing the down-converted value in the specified destination location.

8. 发明授权

US10209986B2 Floating point rounding processors, methods, systems, and instructions 有权
公开(公告)号：US10209986B2
公开(公告)日：2019-02-19
申请号：US13976792
申请日：2011-12-22
申请人： Jesus Corbal San Adrian , Cristina S. Anderson , Robert Valentine , Bret Toll , Amit Gradstein , Simon Rubanovich , Benny Eitan
发明人： Jesus Corbal San Adrian , Cristina S. Anderson , Robert Valentine , Bret Toll , Amit Gradstein , Simon Rubanovich , Benny Eitan
IPC分类号： G06F9/30
摘要： A method of an aspect includes receiving a floating point rounding instruction. The floating point rounding instruction indicates a source of one or more floating point data elements, indicates a number of fraction bits after a radix point that each of the one or more floating point data elements are to be rounded to, and indicates a destination storage location. A result is stored in the destination storage location in response to the floating point rounding instruction. The result includes one or more rounded result floating point data elements. Each of the one or more rounded result floating point data elements includes one of the floating point data elements of the source, in a corresponding position, which has been rounded to the indicated number of fraction bits. Other methods, apparatus, systems, and instructions are disclosed.

9. 发明授权

US10162639B2 Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality 有权
公开(公告)号：US10162639B2
公开(公告)日：2018-12-25
申请号：US15912498
申请日：2018-03-05
申请人： Christopher J. Hughes , Mikhail Plotnikov , Andrey Naraikin , Robert Valentine
发明人： Christopher J. Hughes , Mikhail Plotnikov , Andrey Naraikin , Robert Valentine
IPC分类号： G06F9/30 , G06F9/38
摘要： Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.

10. 发明授权

US10162638B2 Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality 有权
公开(公告)号：US10162638B2
公开(公告)日：2018-12-25
申请号：US15912486
申请日：2018-03-05
申请人： Christopher J. Hughes , Mikhail Plotnikov , Andrey Naraikin , Robert Valentine
发明人： Christopher J. Hughes , Mikhail Plotnikov , Andrey Naraikin , Robert Valentine
IPC分类号： G06F9/30 , G06F9/38
摘要： Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.

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