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1. 发明专利

JP2011176047A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011176047A
公开(公告)日：2011-09-08
申请号：JP2010037793
申请日：2010-02-23
申请人： On Semiconductor Trading Ltd , オンセミコンダクター・トレーディング・リミテッド
发明人： YAMADA KATSUO , NOMURA YOJI
IPC分类号： H01L21/02 , H01L21/027 , H01L21/336 , H01L21/76 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To prevent cracks from reaching to an element forming region on the occurrence of the cracks in an SOG film in a trench forming a process mark, an alignment mark or the like.
SOLUTION: The process mark 30C is formed by the pattern of the trenches 31 on the outside of the element forming region 10T of a semiconductor substrate 10. The element forming region 10T and the trenches 31 on the outside thereof are coated with an interlayer dielectric 21. The interlayer dielectric 21 is coated with the SOG films 22 embedding the insides of the trenches 31. An annular polysilicon film 18 surrounding the trenches 31 and the SOG films 22 on the trenches 31 is formed on the surface of the semiconductor substrate 10.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了防止在形成处理标记的沟槽中的SOG膜中出现裂缝时产生裂纹到元件形成区域，对准标记等。解决方案：处理标记30C由半导体衬底10的元件形成区域10T的外侧上的沟槽31的图案形成。元件形成区域10T和其外部的沟槽31涂覆有层间电介质21.层间电介质21涂覆有嵌入沟槽31内部的SOG膜22.围绕沟槽31的环状多晶硅膜18和沟槽31上的SOG膜22形成在半导体衬底的表面上 10.版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2012119559A Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012119559A
公开(公告)日：2012-06-21
申请号：JP2010269155
申请日：2010-12-02
申请人： On Semiconductor Trading Ltd , オンセミコンダクター・トレーディング・リミテッド
发明人： YAMADA KATSUO , YAJIMA MANABU
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L29/41 , H01L29/417
摘要： PROBLEM TO BE SOLVED: To provide a power MOS transistor which reduces contact resistances of a miniaturized N+ type source layer and a source electrode.SOLUTION: A P-type body layer 6 is formed on a surface of an N-type drift layer 2, and an N+type source layer 7 is formed on a surface of the P-type body layer 6. A first contact hole 9 is formed on an interlayer insulating film 8 covering the N+type source layer 7, and a part of the N+type source layer 7 is exposed. A second contact hole 10 is formed from a surface of the N+type source layer 7 exposed to a bottom surface of the first contact hole 9 to the P-type body layer 6. A P+type contact layer 11 is formed on the surface of the P-type body layer 6 exposed to a bottom surface of the second contact hole 10. An N+type layer 7a having a smaller width than the variation width of a mask alignment accuracy in a photolithography process, is formed on the bottom surface of the first contact hole 9 and the first and second holes 9, 10 are filled with a tungsten layer 12 and so on.
摘要翻译：解决的问题：提供降低小型化N +型源极层和源极电极的接触电阻的功率MOS晶体管。解决方案：在N型漂移层2的表面上形成P型体层6，在P型体层6的表面上形成N +型源极层7.第一接触孔9形成在覆盖N +型源极层7的层间绝缘膜8上，并且N +型源极层7的一部分露出。第二接触孔10从暴露于第一接触孔9的底面到N型体层6的N +型源极层7的表面形成.P +型接触层11形成在表面暴露于第二接触孔10的底表面的P型体层6.在底面上形成具有比光刻工艺中的掩模对准精度的变化宽度小的宽度的N +型层7a 的第一接触孔9和第一孔9和第二孔10填充有钨层12等。版权所有（C）2012，JPO＆INPIT

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