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1. 发明申请

WO2010108810A1 LOW-POWER DUAL-EDGE-TRIGGERED STORAGE CELL WITH SCAN TEST SUPPORT AND CLOCK GATING CIRCUIT THEREFOR 审中-公开
标题翻译：具有扫描测试支持和时钟提升电路的低功率双边触发存储单元
公开(公告)号：WO2010108810A1
公开(公告)日：2010-09-30
申请号：PCT/EP2010/053293
申请日：2010-03-15
申请人： OTICON A/S , SALLING, Jacob
发明人： SALLING, Jacob
IPC分类号： H03K3/012 , H03K3/037
CPC分类号： H03K19/0013 , H03K3/012 , H03K3/037
摘要： A storage cell (1) having a pulse generator (5) and a storage element (6) is proposed. The storage element input (7) is connected to receive a data input signal (DIN). The storage element output (9) is connected to provide a data output signal (DOUT). The storage element (6) is operable in one of a data retention state and a data transfer state in response to a storage control signal (SC) received from the pulse generator (5). The pulse generator (5) is connected to receive a clock signal (CK) with rising and falling clock signal edges (13, 14) and is adapted to provide control pulses (15, 16) in the storage control signal (SC). Each control pulse (15, 16) has a leading edge (17) and a trailing edge (18). The control pulses (15, 16) have a polarity suited to invoke the data transfer state on their leading edges (17). The novel feature is that the pulse generator (5) is adapted to initiate a rising-edge control pulse (15) when receiving a rising clock signal edge (13) and to initiate a falling-edge control pulse (16) when receiving a falling clock signal edge (14). In this way, a dual-edge- triggered flip-flop may be made using only combinatorial logic circuitry and one level- or single-edge-triggered storage element (6). The storage cell (1) has low power consumption, facilitates scan testing and can be used by existing design tools and test equipment.
摘要翻译：提出了具有脉冲发生器（5）和存储元件（6）的存储单元（1）。存储元件输入（7）被连接以接收数据输入信号（DIN）。存储元件输出（9）被连接以提供数据输出信号（DOUT）。响应于从脉冲发生器（5）接收的存储控制信号（SC），存储元件（6）可以在数据保持状态和数据传送状态之一中操作。脉冲发生器（5）被连接以接收具有上升和下降时钟信号边沿（13,14）的时钟信号（CK），并且适于在存储控制信号（SC）中提供控制脉冲（15,16）。每个控制脉冲（15,16）具有前缘（17）和后缘（18）。控制脉冲（15,16）具有适于在其前沿（17）上调用数据传输状态的极性。新颖的特征是脉冲发生器（5）适于在接收到上升时钟信号沿（13）时启动上升沿控制脉冲（15），并且当接收到下降沿时产生下降沿控制脉冲（16）时钟信号边沿（14）。以这种方式，可以仅使用组合逻辑电路和一个电平或单边沿触发的存储元件（6）来制造双边沿触发的触发器。存储单元（1）具有低功耗，便于扫描测试，可以由现有的设计工具和测试设备使用。

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