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1. 发明申请

US20110101491A1 INTEGRATED CIRCUIT PACKAGES INCLUDING HIGH DENSITY BUMP-LESS BUILD UP LAYERS AND A LESSER DENSITY CORE OR CORELESS SUBSTRATE 有权
标题翻译：集成电路封装，包括高密度BUX-LESS BUILD UP层和较低密度芯或无损基板
公开(公告)号：US20110101491A1
公开(公告)日：2011-05-05
申请号：US11860922
申请日：2007-09-25
申请人： OSWALD SKEETE , RAVI MAHAJAN , JOHN GUZEK
发明人： OSWALD SKEETE , RAVI MAHAJAN , JOHN GUZEK
IPC分类号： H01L27/06 , H01L23/498
CPC分类号： H01L25/0652 , H01L21/563 , H01L23/3128 , H01L23/49827 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L25/105 , H01L25/16 , H01L2224/05548 , H01L2224/05573 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/14 , H01L2924/1433 , H01L2924/15174 , H01L2924/15311 , H01L2924/18161 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2224/05599
摘要： In some embodiments, integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate are presented. In this regard, an apparatus is introduced having a first element including a microelectronic die having an active surface and at least one side, an encapsulation material adjacent said at least one microelectronic die side, wherein said encapsulation material includes at least one surface substantially planar to said microelectronic die active surface, a first dielectric material layer disposed on at least a portion of said microelectronic die active surface and said encapsulation material surface, a plurality of build-up layers disposed on said first dielectric material layer, and a plurality of conductive traces disposed on said first dielectric material layer and said build-up layers and in electrical contact with said microelectronic die active surface; and a second element coupled to the first element, the second element including a substrate having a plurality of dielectric material layers and conductive traces to conductively couple conductive contacts on a top surface with conductive contacts on a bottom surface, said conductive contacts on said top surface conductively coupled with said conductive traces of said first element. Other embodiments are also disclosed and claimed.
摘要翻译：在一些实施例中，提出了包括高密度无凸起构建层和较小密度芯或无芯衬底的集成电路封装。在这方面，引入了具有第一元件的装置，该第一元件包括具有活性表面和至少一个侧面的微电子管芯，邻近所述至少一个微电子管芯侧的封装材料，其中所述封装材料包括至少一个表面，所述微电子管芯有源表面，设置在所述微电子管芯有源表面和所述封装材料表面的至少一部分上的第一介电材料层，设置在所述第一介电材料层上的多个堆积层，以及多个导电迹线设置在所述第一介电材料层和所述堆积层上并与所述微电子管芯有源表面电接触; 以及耦合到所述第一元件的第二元件，所述第二元件包括具有多个电介质材料层和导电迹线的衬底，所述导电迹线导电地将顶表面上的导电触点与底表面上的导电触点导电，所述顶表面上的所述导电触点与所述第一元件的所述导电迹线导电耦合。还公开并要求保护其他实施例。

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