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1. 发明专利

ES2341202B1 CIRCUITO MULTIPLICADOR DE UN UNICO BIT CON FUNCION DE AJUSTE DE FASE. 未知
公开(公告)号：ES2341202B1
公开(公告)日：2011-04-08
申请号：ES200800485
申请日：2008-02-21
申请人： OSAKI ELECTRIC CO LTD
发明人： OHHIRA TAKEO , AIKYO YASUAKI , KAWASHIMA NAOTO , GO KAZUNORI
IPC分类号： H03M7/32 , H03K5/00 , H03M1/10

2. 发明专利

ES2341202A1 CIRCUITO MULTIPLICADOR DE UN UNICO BIT CON FUNCION DE AJUSTE DE FASE. 未知
公开(公告)号：ES2341202A1
公开(公告)日：2010-06-16
申请号：ES200800485
申请日：2008-02-21
申请人： OSAKI ELECTRIC CO LTD
发明人： AIKYO YASUAKI , GO KAZUNORI , KAWASHIMA NAOTO , OHHIRA TAKEO
IPC分类号： H03M7/32 , H03K5/00 , H03M1/10
摘要： Circuito multiplicador de un único bit con función de ajuste de fase. Aumenta la resolución del ajuste de fase. Incluye un elemento aritmético de un bit 9 que multiplica señales de un bit dentro del cual las dos señales analógicas se convierten por un elemento de conversión {dl}{sg} 1, con una frecuencia de reloj del elemento aritmético de un bit que se fija a un múltiplo entero de la frecuencia de reloj del elemento de conversión {dl}{sg}, tiene dos elementos de almacenamiento multi-etapa 7 y 8 que almacenan respectivamente señales digitales de un bit, e introducen las salidas de multi-etapas almacenadas dentro del elemento aritmético de un bit, y un elemento de fijación del ajuste de fase 10 que fija las temporizaciones de salida de las dos salidas multi-etapa extraídas de los elementos de almacenamiento multi-etapa en diferentes puntos del tiempo dentro de un período de reloj del elemento de conversión {dl}{sg}; evitando aumentar su frecuencia.

3. 发明专利

ES2341208B1 CIRCUITO REGULADOR DE AMPLITUD DE UN SOLO BIT 未知
公开(公告)号：ES2341208B1
公开(公告)日：2011-05-03
申请号：ES200802050
申请日：2008-07-09
申请人： OSAKI ELECTRIC CO LTD
发明人： OHHIRA TAKEO , AIKYO YASUAKI , KAWASHIMA NAOTO , GO KAZUNORI
IPC分类号： H03M3/02

4. 发明专利

ES2341208A1 CIRCUITO REGULADOR DE AMPLITUD DE UN SOLO BIT 未知
公开(公告)号：ES2341208A1
公开(公告)日：2010-06-16
申请号：ES200802050
申请日：2008-07-09
申请人： OSAKI ELECTRIC CO LTD
发明人： KAWASHIMA NAOTO , GO KAZUNORI , OHHIRA TAKEO , AIKYO YASUAKI
IPC分类号： H03M3/02
摘要： Circuito regulador de amplitud de un solo bit. Para regular la amplitud de una señal digital salida de un convertidor A/D de un esquema de modulación {dl}{sg} que tiene una resolución de N bits con un valor de regulación de amplitud que tiene M dígitos, dado que se debe realizar multiplicaciones de NxM bits, un multiplicador se incrementa en escala, y requiere un número de elementos de circuito y una zona de montaje grande. Una señal de entrada (X) de un modulador {dl}{sg}(2a), representada por una señal de un bit y que sigue siendo la señal de un bit, es multiplicada por un valor de regulación de amplitud de 11 dígitos salido de un registro de valor de regulación de amplitud (2d) por un multiplicador de un solo bit (2c) para regular su amplitud. Así, la amplitud puede ser regulada sin realizar multiplicaciones de una señal de 16 bits (N-bits) o multi-bit con un valor de regulación de amplitud de 11 dígitos (M dígitos) (16x11) como antes. Como resultado, es posible reducir el número de elementos de circuito que incluyen el multiplicador (2c) para reducir la escala de circuito del circuito regulador de amplitud por un factor de N.

5. 发明专利

JP2010008340A Current sensor circuit for coil 有权
标题翻译：电流传感器电路
公开(公告)号：JP2010008340A
公开(公告)日：2010-01-14
申请号：JP2008170536
申请日：2008-06-30
申请人： Osaki Electric Co Ltd , 大崎電気工業株式会社
发明人： KAWASHIMA NAOTO , AIKYO YASUAKI
IPC分类号： G01R19/00 , G01R21/06 , G01R21/127 , G01R22/00
摘要： PROBLEM TO BE SOLVED: To provide a method of measuring current, or the like, wherein an integral value is suppressed to within a predetermined range even if an offset component is included in an input signal of an integrating circuit when an induced voltage signal detected by a coil is integrated and the instantaneous value of current is determined, and a measurement error resulting from the offset component is reduced. SOLUTION: This current sensor circuit integrates the induced voltage signal with a plurality of integrating means with initial values different by a predetermined value, sequentially switches the integrating means with a large initial value to the integrating means with the next larger initial value every predetermined time, and performs an output, thereby converting the offset component into a periodic waveform having a period N times that of a signal to be measured. An instrument such as a watt-hour meter using this is provided. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种测量电流等的方法，其中积分值被抑制在预定范围内，即使当积分电路的输入信号中的偏移分量被包括在感应电压由线圈检测的信号被积分，并且确定电流的瞬时值，并且减少由偏移分量产生的测量误差。解决方案：该电流传感器电路将感应电压信号与多个积分装置进行积分，初始值与预定值不同，顺序地将具有较大初始值的积分装置依次切换到具有下一较大初始值的积分装置并且执行输出，从而将偏移分量转换成具有被测信号的周期N倍的周期波形。提供了使用这样的仪表，例如瓦特计。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2005142877A Single-bit δσ modulation arithmetic circuit 有权
标题翻译：单位DeltaSigma调制算术电路
公开(公告)号：JP2005142877A
公开(公告)日：2005-06-02
申请号：JP2003377796
申请日：2003-11-07
申请人： Osaki Electric Co Ltd , 大崎電気工業株式会社
发明人： KAWASHIMA NAOTO , GO KAZUNORI , AIKYO YASUAKI , FUJISAKA NAOTO
IPC分类号： H03M3/02
摘要： PROBLEM TO BE SOLVED: To solve a problem that it takes a longer time for a conventional single-bit ΔΣ modulation arithmetic circuit to represent the true value of an arithmetic result as adding and multiplying operations by the arithmetic circuit increase in number.
SOLUTION: An addition result z(n) of x
1 (n) and x
2 (n) by a single-bit adder 10 is represented by two equations z(n+1)=(x
1 (n)+x
2 (n))/2 and q(n+1)=q(n) when x
1 (n)+x
2 (n)≠0 and represented by two equations z(n+1)=q(n) and q(n+1)=-q(n) when x
1 (n)+x
2 (n)=0. The single-bit adder 10 directly adds two ΔΣ-modulated one-bit signals x1(n) and x2(n) with an operation clock which is twice as fast as a sampling clock Fs without converting them into multi-bit signals, and outputs the addition result as a one-bit signal z(n).
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题为了解决传统的单位ΔΣ调制运算电路在运算电路的加法和乘法运算数量增加时表示算术结果的真实值所需的时间较长的问题。解决方案：通过单位加法器10的x SB 1（n）和x SB 2（n）的相加结果z（n）由两个等式当x（n + 1）=（x 1 （n）+ x （n））/ 2和q（n + 1）= q （n）+ x SB 2（n）≠0并由两个方程表示z（n + 1）= q（n）和q（n + 1）= -q（n）当x （n）+ x 2时，（n）= 0。单位加法器10将两个ΔΣ调制的一位信号x1（n）和x2（n）直接相加，其运算时钟是采样时钟Fs的两倍，而不将它们转换为多位信号，并且输出加法结果作为一位信号z（n）。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2008020394A Electric power measuring part ic circuit 有权
标题翻译：电力测量部件IC电路
公开(公告)号：JP2008020394A
公开(公告)日：2008-01-31
申请号：JP2006194001
申请日：2006-07-14
申请人： Osaki Electric Co Ltd , 大崎電気工業株式会社
发明人： GO KAZUNORI , KAWASHIMA NAOTO , OHIRA TAKEO , AIKYO YASUAKI
IPC分类号： G01R21/133 , G01R22/00
摘要： PROBLEM TO BE SOLVED: To provide an electric power measuring part IC circuit capable of configuring a variety of watt hour meters. SOLUTION: The IC circuit includes an A/D conversion circuit 11E A/D-converting two voltage signals, an A/D conversion circuit 11C A/D-converting two current signals, multiplication circuits 13e and 13r, a selection circuit 16 having selection switches 161, 162, and 163, cumulative circuits 141, 142, and 143, and a synthesizing circuit 15 synthesizing cumulative results from the respective cumulative circuits. The selection circuit 16 has an output terminal T7 outputting output from the multiplication circuit 13e to the external, an output terminal T8 outputting output from the multiplication circuit 13r to the external, an input terminal T9 inputting an external signal to the second contact of the selection switch 161 and the first contact of the selection switch, and an input terminal T10 inputting an external signal to the second contact of the selection switch 163. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供能够配置各种功率计的电力测量部件IC电路。解决方案：IC电路包括A / D转换电路11E A / D转换两个电压信号，A / D转换电路11C A / D转换两个电流信号，乘法电路13e和13r，选择电路 16，具有选择开关161,162和163，累积电路141,142和143，以及合成电路15，其合成来自各累积电路的累积结果。选择电路16具有从乘法电路13e向外部输出的输出端子T7，将乘法电路13r的输出输出到外部的输出端子T8，将输入外部信号的输入端子T9输入到选择的第二触点开关161和选择开关的第一触点，以及输入端子T10，向选择开关163的第二触点输入外部信号。（C）2008，JPO＆INPIT

8. 发明专利

JP2005303944A Single bit δσ modulation calculation circuit 有权
标题翻译：单位DeltaSigma调制计算电路
公开(公告)号：JP2005303944A
公开(公告)日：2005-10-27
申请号：JP2004121070
申请日：2004-04-16
申请人： Osaki Electric Co Ltd , 大崎電気工業株式会社
发明人： AIKYO YASUAKI , GO KAZUNORI , KAWASHIMA NAOTO
IPC分类号： H03M3/02
摘要： PROBLEM TO BE SOLVED: To solve a problem wherein a frequency of using a single bit adder composing a multiplier is increased with an increase of the number of taps of the multiplier, and a scale of the multiplier becomes large.
SOLUTION: A single bit ΔΣ modulation calculation circuit 20 is provided with a multiplier 21 of 2
2 tap×2
2 tap. The multiplier 21 is composed of four delay circuits 12a-12d, ten exclusive logical sum circuits 13a-13c, 13e, 13g, 13i, 13k, 13m, 13o, and 13p at the first stage and nine 1-bit adders 14a, 14h, 14i-14o at the second to fifth stages. In the multiplier 21, the 1-bit adders 14b-14g shown in a diagram are eliminated, and the multiplier 21 is arranged so that twice weights are assigned to 1-bit signals inputted to the 1-bit adders 14i-14l. The arrangement at the second stage of the 1-bit adders connected in multi-stages is simplified.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：为了解决使用构成乘法器的单位加法器的频率随着乘法器的抽头数量的增加而增加的问题，乘法器的比例变大。解决方案：单位ΔΣ调制计算电路20设置有2 2 抽头×2 2 抽头的乘法器21。乘法器21由第一级的四个延迟电路12a-12d，十个异或逻辑和电路13a-13c，13e，13g，13i，13k，13m，13o和13p以及九个1位加法器14a，14h， 14i-14o在第二到第五阶段。在乘法器21中，省略了图中所示的1位加法器14b-14g，并且乘法器21被布置为使得输入到1位加法器14i-14l的1位信号分配了两个权重。在多级连接的1位加法器的第二级的布置被简化。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2014115183A Ac signal level/dc signal level conversion device and ac signal level/frequency conversion device using the device 有权
标题翻译：交流信号电平/直流信号电平转换装置和交流信号电平/频率转换装置使用装置
公开(公告)号：JP2014115183A
公开(公告)日：2014-06-26
申请号：JP2012269198
申请日：2012-12-10
申请人： Osaki Electric Co Ltd , 大崎電気工業株式会社
发明人： AIKYO YASUAKI , OHIRA TAKEO , KAWASHIMA NAOTO , KUROSAWA WATARU
IPC分类号： G01R21/133
摘要： PROBLEM TO BE SOLVED: To accurately measure the amount of AC power without using an LPF.SOLUTION: An average value calculation circuit 11 calculates an average power value in each period, and outputs the average value in a previous period from a latch circuit 12 for a current period. A comparator 14 is applied with the average value in the previous period at one input terminal, compares this average value with a signal applied to the other input terminal, and controls switching means 15 so as to output smaller one of the signals. An adder 16 subtracts the signal outputted from the switching means, from the signal applied to the other input terminal of the comparison means, and a previous value holding circuit 17 stores a signal obtained by the subtraction and outputs a signal obtained by the subtraction in the previous sampling. An adder 13 adds the signal from the previous value holding circuit 17 and a power value at the current sampling time and applies a result to the other input terminal of the comparator. Since the output of the switching circuit 15 becomes constant, an integrated value Wh2 obtained by an integrator 105 is linearly increased to avoid the occurrence of variation in period of a pulse train from a pulsing circuit 106.
摘要翻译：要解决的问题：在不使用LPF的情况下精确地测量AC电力。解算：平均值计算电路11计算每个周期中的平均功率值，并将前一时段中的平均值从锁存电路12输出当前时期。比较器14在一个输入端施加前一周期中的平均值，将该平均值与施加到另一个输入端的信号进行比较，并控制开关装置15以输出较小的一个信号。加法器16从施加到比较装置的另一输入端的信号中减去从切换装置输出的信号，并且先前值保持电路17存储通过减法获得的信号，并将通过减法获得的信号输出到以前的抽样。加法器13将来自先前值保持电路17的信号和当前采样时间的功率值相加，并将结果施加到比较器的另一输入端。由于开关电路15的输出变为恒定，因此积分器105获得的积分值Wh2被线性地增加，以避免脉冲串从脉冲电路106发生的周期变化。

10. 发明专利

JP2008211722A Single bit amplitude adjusting circuit 有权
标题翻译：单位AMPLITUDE调节电路
公开(公告)号：JP2008211722A
公开(公告)日：2008-09-11
申请号：JP2007048646
申请日：2007-02-28
申请人： Osaki Electric Co Ltd , 大崎電気工業株式会社
发明人： KAWASHIMA NAOTO , GO KAZUNORI , OHIRA TAKEO , AIKYO YASUAKI
IPC分类号： H03M3/02
摘要： PROBLEM TO BE SOLVED: To solve a problem of enlargement of scale of a multiplier because of necessary multiplication of N×M bits, and the need of many circuit elements and its large mounting area when amplitude adjustment of a digital signal outputted from an A/D converter with resolution of N bits in a ΔΣ modulation method is carried out with an amplitude adjustment value of M digits.
SOLUTION: An input signal X expressed as a one-bit signal from a ΔΣ modulator 2a is multiplied in still one-bit state by an amplitude adjustment value of 11 digits, which is outputted from amplitude adjustment value register 2d, through a single bit multiplier 2c so that its amplitude is adjusted. Then, amplitude adjustment can be performed without carrying out multiplication (16×11) with a multiple bit signal of 16(N) bits and an amplitude adjustment value of 11(M) digits in a conventional way. In this way, the number of circuit elements, which constitute the multiplier 2c, can be reduced, and the circuit scale of the amplitude adjusting circuit can be reduced to 1/N.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了解决由于N×M位的必要乘法而引起的乘法器规模的扩大的问题，以及当输出的数字信号的幅度调整时需要许多电路元件和大的安装面积在ΔΣ调制方式中，具有N位分辨率的A / D转换器以幅度调整值M位数进行。解决方案：将来自ΔΣ调制器2a的作为一比特信号表示的输入信号X在静态1比特状态下被从振幅调整值寄存器2d输出的幅度调整值为11位，通过单位乘法器2c使其幅度被调整。然后，可以以常规方式对16位（N）位的多位信号和幅度调整值11（M）位进行乘法运算（16×11）而进行幅度调整。以这种方式，可以减少构成乘法器2c的电路元件的数量，并且可以将幅度调整电路的电路规模减小到1 / N。版权所有（C）2008，JPO＆INPIT

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