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1. 发明申请

WO2014099887A1 DISTRIBUTED CACHE COHERENCY DIRECTORY WITH FAILURE REDUNDANCY 审中-公开
标题翻译：分布式高速缓存目录与故障冗余
公开(公告)号：WO2014099887A1
公开(公告)日：2014-06-26
申请号：PCT/US2013/075622
申请日：2013-12-17
申请人： ORACLE INTERNATIONAL CORPORATION
发明人： WICKI, Thomas, M. , PHILLIPS, Stephen, E. , ANESHANSLEY, Nicholas, E. , SIVARAMAKRISHNAN, Ramaswamy , LOEWENSTEIN, Paul, N.
IPC分类号： G06F12/08 , G06F11/07
CPC分类号： G06F12/0831 , G06F11/07 , G06F11/14 , G06F12/0824
摘要： A system includes a number of processors with each processor including a cache memory. The system also includes a number of directory controllers coupled to the processors. Each directory controller may be configured to administer a corresponding cache coherency directory. Each cache coherency directory may be configured to track a corresponding set of memory addresses. Each processor may be configured with information indicating the corresponding set of memory addresses tracked by each cache coherency directory. Directory redundancy operations in such a system may include identifying a failure of one of the cache coherency directories; reassigning the memory address set previously tracked by the failed cache coherency directory among the non-failed cache coherency directories; and reconfiguring each processor with information describing the reassignment of the memory address set among the non-failed cache coherency directories.
摘要翻译：系统包括多个处理器，每个处理器包括高速缓冲存储器。该系统还包括耦合到处理器的多个目录控制器。每个目录控制器可以被配置为管理对应的高速缓存一致性目录。每个高速缓存一致性目录可以被配置为跟踪相应的一组存储器地址。每个处理器可以配置有指示由每个高速缓存一致性目录跟踪的对应的一组存储器地址的信息。这种系统中的目录冗余操作可以包括识别高速缓存一致性目录之一的故障; 重新分配先前由非故障高速缓存一致性目录中的失败的高速缓存一致性目录跟踪的存储器地址集; 以及用描述非故障高速缓存一致性目录中的存储器地址集的重新分配的信息来重新配置每个处理器。

2. 发明公开

EP2936320A1 DISTRIBUTED CACHE COHERENCY DIRECTORY WITH FAILURE REDUNDANCY 有权
标题翻译：与错误冗余分布式缓存相干LIST
公开(公告)号：EP2936320A1
公开(公告)日：2015-10-28
申请号：EP13818113.6
申请日：2013-12-17
申请人： Oracle International Corporation
发明人： WICKI, Thomas, M. , PHILLIPS, Stephen, E. , ANESHANSLEY, Nicholas, E. , SIVARAMAKRISHNAN, Ramaswamy , LOEWENSTEIN, Paul, N.
IPC分类号： G06F12/08 , G06F11/07
CPC分类号： G06F12/0831 , G06F11/07 , G06F11/14 , G06F12/0824
摘要： A system includes a number of processors with each processor including a cache memory. The system also includes a number of directory controllers coupled to the processors. Each directory controller may be configured to administer a corresponding cache coherency directory. Each cache coherency directory may be configured to track a corresponding set of memory addresses. Each processor may be configured with information indicating the corresponding set of memory addresses tracked by each cache coherency directory. Directory redundancy operations in such a system may include identifying a failure of one of the cache coherency directories; reassigning the memory address set previously tracked by the failed cache coherency directory among the non-failed cache coherency directories; and reconfiguring each processor with information describing the reassignment of the memory address set among the non-failed cache coherency directories.

3. 发明授权

EP2936320B1 DISTRIBUTED CACHE COHERENCY DIRECTORY WITH FAILURE REDUNDANCY 有权
公开(公告)号：EP2936320B1
公开(公告)日：2018-11-21
申请号：EP13818113.6
申请日：2013-12-17
申请人： Oracle International Corporation
发明人： WICKI, Thomas, M. , PHILLIPS, Stephen, E. , ANESHANSLEY, Nicholas, E. , SIVARAMAKRISHNAN, Ramaswamy , LOEWENSTEIN, Paul, N.
IPC分类号： G06F12/0817 , G06F12/0831 , G06F11/14
CPC分类号： G06F12/0831 , G06F11/07 , G06F11/14 , G06F12/0824
摘要： A system includes a number of processors with each processor including a cache memory. The system also includes a number of directory controllers coupled to the processors. Each directory controller may be configured to administer a corresponding cache coherency directory. Each cache coherency directory may be configured to track a corresponding set of memory addresses. Each processor may be configured with information indicating the corresponding set of memory addresses tracked by each cache coherency directory. Directory redundancy operations in such a system may include identifying a failure of one of the cache coherency directories; reassigning the memory address set previously tracked by the failed cache coherency directory among the non-failed cache coherency directories; and reconfiguring each processor with information describing the reassignment of the memory address set among the non-failed cache coherency directories.

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