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1. 发明申请

WO1991000616A1 WIRING STRUCTURE OF SEMICONDUCTOR CHIP 审中-公开
标题翻译：半导体芯片接线结构
公开(公告)号：WO1991000616A1
公开(公告)日：1991-01-10
申请号：PCT/JP1990000424
申请日：1990-03-29
申请人： OKI ELECTRIC INDUSTRY CO., LTD. , FUKUDA, Yasuhiro , SUGAHARA, Tetsuhiko , HIRASHITA, Norio , MATSUO, Mitsuhiro , SAITO, Minoru , KOBAYAKAWA, Masayuki , YOKOYAMA, Fumitaka
发明人： OKI ELECTRIC INDUSTRY CO., LTD.
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： In order to prevent a relatively wide aluminum wiring layer (12) such as a power source wiring or a ground wiring formed on a semiconductor substrate (11) from being corroded by the sliding and, in the case of a multilayer interconnection, to prevent the lower-layer wiring from being broken by the sliding of the upper-layer aluminum wiring (12) and to prevent the generation of voids in the lower-layer aluminum wiring layer caused by moisture under the wide metal wiring layer, the relatively wide wiring layer (12) is devided in such a manner that each wiring layer after being divided will have a width of greater than 10 νm but smaller than 40 νm.

2. 发明申请

WO1991001568A1 PROCESS FOR FABRICATING SEMICONDUCTOR DEVICES 审中-公开
标题翻译：制造半导体器件的工艺
公开(公告)号：WO1991001568A1
公开(公告)日：1991-02-07
申请号：PCT/JP1990000821
申请日：1990-06-25
申请人： OKI ELECTRIC INDUSTRY CO., LTD. , HIRASHITA, Norio
发明人： OKI ELECTRIC INDUSTRY CO., LTD.
IPC分类号： H01L21/28
CPC分类号： H01L21/76886 , H01L21/28518
摘要： A process for fabricating semiconductor devices such as MOS integrated circuits, in which a plurality of diffusion layers formed by doping a substrate with impurities at high concentration are connected together using a high-melting metal silicide. A silicon layer (108) under a non-doped layer is formed on the substrate (100) to be processed, and a high-melting metal layer (109) is formed on the silicon layer (108). The high-melting metal layer (109) is reacted with the silicon layer (108) to form the high-melting metal silicide (112) that connect the diffusion layers together. Thus, the high-melting metal silicide layer (112) can be stably formed suppressing the junction leakage as low as possible.
摘要翻译：用于制造诸如MOS集成电路的半导体器件的工艺，其中通过使用高熔点金属硅化物将以高浓度的杂质掺杂的衬底形成的多个扩散层连接在一起。在待加工的基板（100）上形成非掺杂层下的硅层（108），在硅层（108）上形成高熔点金属层（109）。高熔点金属层（109）与硅层（108）反应形成将扩散层连接在一起的高熔点金属硅化物（112）。因此，可以稳定地形成高熔点金属硅化物层（112），以尽可能低地抑制结漏电。

3. 发明申请

WO1994010705A1 INPUT/OUTPUT PROTECTIVE CIRCUIT 审中-公开
标题翻译：输入/输出保护电路
公开(公告)号：WO1994010705A1
公开(公告)日：1994-05-11
申请号：PCT/JP1993001557
申请日：1993-10-28
申请人： OKI ELECTRIC INDUSTRY CO., LTD. , KATAKURA, Yoshiaki , FUKUDA, Yasuhiro
发明人： OKI ELECTRIC INDUSTRY CO., LTD.
IPC分类号： H01L29/784
CPC分类号： H01L27/0251
摘要： The cathode of an input protective diode (40) is connected directly to the drain (30D) of an input protective MOS transistor (30). The source (30S), the gate (30G), and the anode of the input protection diode (40) are grounded. Thus, overvoltage inputted from the external terminal is received by the cathode of the diode (40) and the drain (30D) before such a voltage is transferred to the internal circuit of a semiconductor device. Hence there is no increase in the junction capacitance of the input protective diode due to the pattern of the diode (40). The voltage value at which the input protective MOS transistor (30) conducts can be lowered because the input protective diode (40) breaks down by overvoltage before it reaches the internal circuit. As a result, it is possible to achieve reliable input protection at a high speed. Also, since the input terminal can be connected directly to the drain (30D) of the input protective MOS transistor (30), the input protective circuit shown is applicable to an output protection circuit and an output MOS transistor, thus making it possible to protect the internal output circuit reliably.
摘要翻译：输入保护二极管（40）的阴极直接连接到输入保护MOS晶体管（30）的漏极（30D）。源极（30S），栅极（30G）和输入保护二极管（40）的阳极接地。因此，在将这样的电压传送到半导体器件的内部电路之前，从外部端子输入的过电压被二极管（40）的阴极和漏极（30D）接收。因此，由于二极管（40）的图案，输入保护二极管的结电容没有增加。由于输入保护二极管（40）在到达内部电路之前由于过电压而损坏，所以输入保护MOS晶体管（30）导通的电压值可能降低。结果，可以高速地实现可靠的输入保护。此外，由于输入端子可以直接连接到输入保护MOS晶体管（30）的漏极（30D），因此所示的输入保护电路可应用于输出保护电路和输出MOS晶体管，从而可以保护内部输出电路可靠。

4. 发明申请

WO1997015120A1 ERROR CORRECTING ENCODER, ERROR CORRECTING DECODER, AND COMMUNICATION SYSTEM 审中-公开
标题翻译：编码器错误校正，错误修正解码器和通信系统
公开(公告)号：WO1997015120A1
公开(公告)日：1997-04-24
申请号：PCT/JP1996002985
申请日：1996-10-15
申请人： OKI ELECTRIC INDUSTRY CO., LTD. , ITOH, Katsutoshi , HOSODA, Kenichiro
发明人： OKI ELECTRIC INDUSTRY CO., LTD.
IPC分类号： H03M13/00
CPC分类号： H03M13/35 , H04L2001/0098
摘要： The error detecting and correcting ability in signal transmission is improved without lowering the transmission efficiency. When a classifying circuit (101) receives information symbols from a voice encoding device, the classifying circuit (101) classifies the symbols according to a classifying definition and feeds the information symbols of the most important class 0 to a CRC calculating circuit (102) and a blocking circuit (103), feeds the information symbols of the second important class 1 to a blocking circuit (105), and feeds the information symbols of the third important class 1 directly to an interleave circuit (107). The CRC calculating circuit (102) finds error detecting information about the information symbols of class 1 fed from the classifying circuit (101), generates data to which the error detecting information is added, and feeds the data to the class-0 blocking circuit (103). The circuit (103) encodes an error-corrected block from the data including the error detecting information and class-0 data.
摘要翻译：在不降低传输效率的情况下，提高了信号传输中的误差检测和纠正能力。当分类电路（101）从语音编码装置接收信息符号时，分类电路（101）根据分类定义对符号进行分类，并将最重要类别0的信息符号馈送到CRC计算电路（102）和阻塞电路（103）将第二重要类别1的信息符号馈送到分块电路（105），并将第三重要类别1的信息符号直接馈送到交织电路（107）。 CRC计算电路（102）发现关于从分类电路（101）馈送的类别1的信息符号的错误检测信息，生成添加了错误检测信息的数据，并将数据馈送到0类阻塞电路 103）。电路（103）从包括错误检测信息和0类数据的数据中对错误校正的块进行编码。

5. 发明申请

WO1994000915A1 BIT ERROR COUNTER AND ITS COUNTING METHOD, AND SIGNAL IDENTIFYING DEVICE AND ITS IDENTIFYING METHOD 审中-公开
标题翻译：位错误计数器及其计数方法和信号识别装置及其识别方法
公开(公告)号：WO1994000915A1
公开(公告)日：1994-01-06
申请号：PCT/JP1993000831
申请日：1993-06-21
申请人： OKI ELECTRIC INDUSTRY CO., LTD. , ABE, Masami
发明人： OKI ELECTRIC INDUSTRY CO., LTD.
IPC分类号： H03M13/12
CPC分类号： H04L1/208 , H03M13/00 , H03M13/23 , H03M13/3961 , H03M13/41 , H04L1/20
摘要： A device and method for counting bit errors in the received signal in digital communication, and a device and method for judging whether received signal is aural signal or control signal and for outputting identification signal, the number of errors, and decoded signal. Generally in bit error counters, there is a problem that an exact error rate cannot be calculated if an error that is incorrectable is included in a decoded signal. To overcome the problem, a status monitoring unit (22) is provided, which outputs a predetermined error rate utilizing information in the decoding process if an error is included in the decoded signal. Further, an error detection unit (28) is provided, which outputs a predetermined error rate if an error is included in the decoded signal. In identification devices, there is a problem that signal cannot be identified if an error that is undetectable is included, because the kind of the input signal is identified based on the result of error detection. To solve this problem, a signal identification unit (1206) is provided, which identifies the input signal based on the error detection result, the decoding result, and the number or errors.
摘要翻译：一种用于对数字通信中的接收信号中的比特错误进行计数的装置和方法，以及用于判断接收信号是听觉信号还是控制信号并用于输出识别信号，误差数目和解码信号的装置和方法。通常在位错误计数器中，存在如下问题：如果解码信号中包含不正确的错误，则不能计算精确的错误率。为了克服这个问题，提供了状态监视单元（22），如果在解码信号中包含错误，则利用解码处理中的信息输出预定的错误率。此外，提供错误检测单元（28），如果解码信号中包含错误，则输出预定的错误率。在识别装置中，由于根据错误检测结果来识别输入信号的种类，所以存在不能识别出不可检测的误差的信号的问题。为了解决这个问题，提供了一种信号识别单元（1206），其基于错误检测结果，解码结果以及数量或错误来识别输入信号。

6. 发明申请

WO1991020051A1 MICROCOMPUTER PROVIDED WITH BUILT-IN CONVERTER 审中-公开
标题翻译： MICROCOMPUTER提供与内置转换器
公开(公告)号：WO1991020051A1
公开(公告)日：1991-12-26
申请号：PCT/JP1991000774
申请日：1991-06-10
申请人： OKI ELECTRIC INDUSTRY CO., LTD. , KOBAYASHI, Jiro , SUWABE, Satoru , ABE, Syunji
发明人： OKI ELECTRIC INDUSTRY CO., LTD.
IPC分类号： G06F15/78
CPC分类号： G06F3/05 , G06F15/7842
摘要： A microcomputer provided with a built-in converter, provided with a CPU (10) which processes digital signals according to program instructions and a converter (30) (an AD or a DA converter) which, for the input or output of the CPU (10), converts an analog signal to a digital signal, or vice versa, has a conversion controlling circuit (40) which controls the operation of the converter (30) according to the controlling output of the CPU (10) and outputs an operation stopping signal to the CPU (10) in a specified period of the operation of the converter (30) (e.g., a period affecting the conversion accuracy of the converter during the converting operation thereof).

7. 发明申请

WO1991018418A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：WO1991018418A1
公开(公告)日：1991-11-28
申请号：PCT/JP1991000655
申请日：1991-05-17
申请人： OKI ELECTRIC INDUSTRY CO., LTD. , KITA, Akio
发明人： OKI ELECTRIC INDUSTRY CO., LTD.
IPC分类号： H01L27/10
CPC分类号： H01L27/10808 , H01L27/1082
摘要： In a semiconductor memory device having cells of one-transistor one-capacitor type, a switching transistor (21) is sandwiched between a capacitor (13) and a bit line (29).
摘要翻译：在具有单晶体管单电容器型的单元的半导体存储器件中，开关晶体管（21）夹在电容器（13）和位线（29）之间。

8. 发明申请

WO1991015812A1 TONER CONTAINER AND ELECTROPHOTOGRAPHIC PRINTER USING THE SAME 审中-公开
标题翻译：调色剂容器和使用它的电子打印机
公开(公告)号：WO1991015812A1
公开(公告)日：1991-10-17
申请号：PCT/JP1991000443
申请日：1991-04-03
申请人： OKI ELECTRIC INDUSTRY CO., LTD. , KIKUCHI, Hiroshi , OTA, Yukio , KOGA, Yoshitomo , OBARA, Kazuki , MOMIYAMA, Yoshiharu , NAKAJIMA, Shigeki , MATSUDA, Kiyoshi , ONO, Hisao
发明人： OKI ELECTRIC INDUSTRY CO., LTD.
IPC分类号： G03G15/08
CPC分类号： G03G15/0868 , G03G2215/0665 , G03G2215/0675 , G03G2215/0685 , Y10S222/01
摘要： The structure of a toner cartridge used for an electrophotographic printer is detachably attached to the printer. A rotary stirrer member (4) is provided in contact with the inner walls of a cartridge (100) in order to reliably stirr the toner stored in the toner cartridge (100). The rotary stirrer member (4) is rotated by a gear (5) that is rotated by an external driving force.

9. 发明申请

WO1991006429A1 WIRE DRIVING MECHANISM 审中-公开
标题翻译：电线驱动机构
公开(公告)号：WO1991006429A1
公开(公告)日：1991-05-16
申请号：PCT/JP1990001382
申请日：1990-10-26
申请人： OKI ELECTRIC INDUSTRY CO., LTD. , ANDOU, Hirokazu , TATSUKAMI, Masahiro , TANUMA, Jiro , KIKUCHI, Hiroshi , KAMIMURA, Katsuya , KOYAMA, Tatsuya , SHIMOMURA, Tatsuhiko
发明人： OKI ELECTRIC INDUSTRY CO., LTD.
IPC分类号： B41J02/295
CPC分类号： B41J2/295
摘要： A wire driving mechanism which is used for a wire dot printing head and uses a piezoelectric device or a magnetostrictive device as a driving source. To obtain a satisfactory printing quality with a simple mechanism, this mechanism has two arms (3a, 3b) disposed in parallel with each other, with one of the ends of each arm being fixed, and rotated by elastic force of an elastic driving source (5). This rotation provides a displacement quantity obtained by magnifying the deformation quantity of the driving source to the free end of each arm. This displacement quantity is applied in a staggered arrangement to both sides of a driving member (8) through a pair of support plates (6a, 6b) so as to rotate the driving member and to deliver the wire (7) in a printing direction.

10. 发明申请

WO1991006119A1 METHOD OF PRODUCING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES 审中-公开
标题翻译：生产半导体集成电路器件的方法
公开(公告)号：WO1991006119A1
公开(公告)日：1991-05-02
申请号：PCT/JP1990001321
申请日：1990-10-12
申请人： OKI ELECTRIC INDUSTRY CO., LTD. , MATSUSHITA, Ikuya
发明人： OKI ELECTRIC INDUSTRY CO., LTD.
IPC分类号： H01L21/76
CPC分类号： H01L21/3086 , H01L21/763
摘要： The method according to this invention comprises a step of forming a three-layer film consisting of a first silicon nitride film (102), a first silicon oxide film (103) and a second silicon nitride film (104) on a portion of a silicon substrate (101), and further forming a third silicon nitride film (106) on the side walls of the three-layer film; a step of forming a first groove having nearly vertical side walls in the exposed silicon substrate (101) by etching, and filling the first groove with a silicon oxide film (108); and a step of removing the second and third silicon nitride films (104, 106) and forming a second groove (111) having side walls that are nearly perpendicular to the exposed silicon substrate (101). Therefore, the second groove (111) that serves as a trench is formed at an end of the silicon oxide film (108) in the field region (107) by the self-alignment to come in direct contact with an element-forming region (115). Further, the width of groove becomes equal to the width of the third silicon nitride film (106) which is constant, and parasitic capacitance becomes the smallest between the collector and substrate.

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