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1. 发明专利

JPS5528111A COMPETITION PREVENTING SYSTEM 失效
公开(公告)号：JPS5528111A
公开(公告)日：1980-02-28
申请号：JP9912878
申请日：1978-08-16
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： NOJIMA HIROMI , SHINTANI HIROSHI , USHIKI TATSUO , YAZAWA KATSUHIKO , FUJITA HIROSHI , FUNAKI TETSUJI
IPC分类号： G06F13/14 , G06F9/00 , G06F15/16 , G06F15/177 , H04Q3/545
摘要： PURPOSE:To keep awaiting the transfer from other, by adding the function clearing the state of transfer to other, when the transfre between central processing units or that between the central processing unit and the maintenance panel unit is made. CONSTITUTION:While the maintenance panel of the central processing unit CCO is controlled, it is detected that flip flop (FF) 210 is set or reset. If FF210 is set, the transfer is kept waited with the microprogram. If reset the central processing unit CCO sets FF 211 during mate control of CCO with the signal of 207 and FF311 during mate control of CC1 via 28-18, and suppresses the transfer request from the maintenance panel unit CNSO to the central processing unit CCO with the signal of 20-12 in hardware manner. Similarly, CC1 suppresses the transfer request from CNS1 to CC1 with the signal of 30-130.

2. 发明专利

JPS58151164A SWITCHING SYSTEM OF SYSTEM 失效
公开(公告)号：JPS58151164A
公开(公告)日：1983-09-08
申请号：JP3241082
申请日：1982-03-03
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： OGAWA YOUICHI , HIROKAWA YUUJI , YOSHIHIRO FUMITAKA , MIURA MASAMI , FUNAKI TETSUJI
IPC分类号： H04M3/22 , H04M3/24 , H04Q3/545
摘要： PURPOSE:To prevent the system-down due to the failure in a switching circuit, by providing a switching circuit corresponding to the system of a channel controller and connecting the circuit to a channel device by duplicating the system at the channel device side of each switching circuit. CONSTITUTION:In controlling a channel device SP from a central controller CC0 via a channel controller SPC0, control is done so as not to activate an output transistor (TR) of a signal distributor SD from the CC0, and contacts tr0, 1 switching relays TR0,1 are selected as shown in Figure. If a switching unit TRU0 is failed to be disconnected, the output TR of the SD is activated from a CC1 and the SP is controlled in the path of CC1 SPC1 tr1 SP and the TRU0 is exchanged, then no system-down takes place. If the TRUi is failed, the exchange of the TRU1 is done without causing system-down similarly.

3. 发明专利

JPS5525870A ACCESS METHOD OF MAGNETIC BUBBLE UNIT 失效
公开(公告)号：JPS5525870A
公开(公告)日：1980-02-23
申请号：JP9894378
申请日：1978-08-14
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO
发明人： FUNAKI TETSUJI , KOBAYASHI KAZUO , NUNOTANI MASAKATSU , SAKATA HIRONOBU
IPC分类号： G11C11/14 , G11C19/08
摘要： PURPOSE:To attain unit-by-unit expansion and continuous access by assigning continuous addresses to chips among different mounting units. CONSTITUTION:For example, each major loop is provided with 128 information minor loops and several stand-by loops, each chip of two 256-bit words consists of a couple of major loops, and each unit is composed of two these chips. In this case, bits S0 to S7 of control word CCW are converted to generate addresses A0 to A9 in major loops. At the time of address assignment, the identical-stage chip of each unit is given the same number and in case of the two-unit constituion, a chip is assigned by bit S18 of CCW while a unit is assigned by bit S8; in mounting, the chip address is made ''0'' to operate units 0 and 1 in parallel and at every time when a magnetic bubble turns a half time on the minor loop, it is transferred onto the major loop to read or write the information of the bubble, so that the purpose will be attained.

4. 发明专利

JPS5525175A CONTROL SYSTEM OF INPUTTOUTPUT DEVICE 失效
公开(公告)号：JPS5525175A
公开(公告)日：1980-02-22
申请号：JP9887078
申请日：1978-08-14
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： TOJIYAMA TAKASHI , USHIKI TATSUO , FUNAKI TETSUJI
IPC分类号： G06F13/42 , G06F3/00 , G06F9/52 , G06F15/16 , G06F15/177
摘要： PURPOSE:To make the synchronization of input-output processes possible by correcting the dispertion of an answer signal from an input-output device by the CUPs of both systems by exchanging the answer signals from the input-output devices between CPUs. CONSTITUTION:To input-output device 1, master system CUP2 and slave system CUP3 are connected and the order is sent out from CUP1 to device 1. When an answer signal is recieved by CPUs 2 and 3, the answer signal from device 1 is latched by FFs 4 and 5 provided to CPUs 2 and 3 and delayed by delay circuits 6 and 7 synchronized by the clock. Further, FFs 4 and 5 are reset by the outputs delayed by circuits 6 and 7 and the outputs of FFs 4 and 5 are corrected to the fixed pulse width synchronized by the clock. Then the outputs of circuits 6 and 7 of a fixed pulse width are supplied to multiplexers 8 and 9 and the output of circuit 6 of CPU2 is selected, thereby outputting a synchronized answer signal.

5. 发明专利

JP2001356829A CURRENT MIRROR CIRCUIT 失效
公开(公告)号：JP2001356829A
公开(公告)日：2001-12-26
申请号：JP2000178466
申请日：2000-06-14
申请人： FUJITSU LTD , FUJITSU VLSI LTD
发明人： WATAI TAKAHIRO , FUNAKI TETSUJI
IPC分类号： G05F3/26 , H03F1/02 , H03F3/343
摘要： PROBLEM TO BE SOLVED: To provide a current mirror circuit for supplying plural bias currents or bias currents whose current ratio is large in an integrated circuit capable of reducing the occupancy area on arrangement, and reducing current consumption. SOLUTION: Inter-input/output NPN type bi-polar transistors constituting each current mirror circuit unit CM11, CM12, CM14, and CM18 are made the same so that the current mirror circuit units having the minimum number of constituting transistors can be serially connected across plural stage while output currents equal to inputted reference currents can be outputted. Thus, it is possible to allow the current input itself to have double current amplifying effects by adding the reference currents inputted to each stage to the output currents. Therefore, it is possible to constitute the current mirror circuit having the minimum number of constituting transistors capable of outputting binary weighted currents.

6. 发明专利

JPH09162721A CURRENT SWITCHING TYPE LOGIC CIRCUIT 失效
公开(公告)号：JPH09162721A
公开(公告)日：1997-06-20
申请号：JP31763895
申请日：1995-12-06
申请人： FUJITSU LTD
发明人： HAYAKAWA ATSUSHI , FUNAKI TETSUJI
IPC分类号： H03K19/003 , H03F3/45 , H03K17/14 , H03K17/60 , H03K19/086
摘要： PROBLEM TO BE SOLVED: To operate the logic circuit under a low power supply voltage by avoiding a process error and effect of an operating temperature. SOLUTION: A base of a 1st differential transistor(TR) Q5 is connected to an emitter of a 1st emitter follower TR Q3 via a 1st emitter resistor R11 , a base of a 2nd differential transistor(TR) Q6 is connected to an emitter of a 2nd emitter follower TR Q4 via a 2nd emitter resistor R12 , and a 2nd constant current source 11 supplying an emitter current to the 1st and 2nd emitter follower TRs Q3 , Q4 is configured by a current mirror circuit. Furthermore, the resistance of the 1st emitter resistor R11 and the 2nd emitter resistor R12 is selected nearly twice the resistance of a load resistor of a reference current side TR Q10 of the current mirror circuit. A base-emitter voltage of the TR of the current mirror circuit cancels the base-emitter voltage of the 1st or 2nd emitter follower TR Q3 or Q4 and the base-emitter voltage of the 1st or 2nd differential TR Q5 or Q5 .

7. 发明专利

JPH06112405A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH06112405A
公开(公告)日：1994-04-22
申请号：JP25825092
申请日：1992-09-28
申请人： FUJITSU LTD
发明人： WATAI TAKAHIRO , FUNAKI TETSUJI , TANAKA HIROKAZU
IPC分类号： H01L27/04 , H01L21/822
摘要： PURPOSE:To transmit a signal without attenuation by a method wherein the same signal is given to the electrode to be connected to a reverse conductive type semiconductor layer and the electrode to be connected to one-conductivity type semiconductor region. CONSTITUTION:CM is the M0S capacitor part which becomes the main capacitor part in the MOS structure consisting of a metal-side electrode 10, an insulating layer 7 and a p-type diffusion layer 6. CS1 is a parasitic capacitor part consisting of a p-n junction capacitor which is generated between the p-type diffusion layer 6 and an n-type epitaxial layer 3, and CS2 is a parasitic capacitor part consisting of a p-n junction capacitor of the conductivity type opposite to that of the CS1 generating between an n type buried diffusion layer 2 and a p-type substrate l. When the same signal is given to A and B terminals, no current is allowed to flow on the capacitor CS1, because the voltage added to both ends of the capacitor CS1 is not changed. As a result, the signal given to the B terminal is transmitted to the C terminal. Accordingly, the C terminal is not subjected to the parasitic effect of parasitic capacitor against the substrate.

8. 发明专利

JPH04129409A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH04129409A
公开(公告)日：1992-04-30
申请号：JP25252190
申请日：1990-09-20
申请人： FUJITSU LTD
发明人： TANAKA HIROKAZU , FUNAKI TETSUJI , HAYAKAWA ATSUSHI
IPC分类号： H03F1/30 , H03F3/34 , H03F3/347 , H03F3/45
摘要： PURPOSE:To increase the operating speed of the signal processing circuit by using a heat element so as to control the electric characteristic of a semiconductor element apart from the heat element. CONSTITUTION:The signal processing circuit 1 is provided with a semiconductor element 2 having an electric characteristic in response to temperature and a heat element 3 is provided close to the semiconductor element 2 and generates or absorbs a heat in response to a supply current. Then a control circuit 4 supplies a current in response to an input signal or an output signal of the signal processing circuit 1 or a current in response to an external signal of the signal processing circuit 1 to change the characteristic of the signal processing circuit 1 to a desired characteristic. That is, since the heat element 3 controls the electric characteristic of the semiconductor element 2 apart from the heat element 3, it is not required to connect the heat element 3 to the input terminal and the output terminal of the signal processing circuit 1 to decrease the capacity of the signal processing circuit 1. Thus, the operating speed of the signal processing circuit 1 is quickened.

9. 发明专利

JPH0332137A SIGNAL TRANSMITTER 失效
公开(公告)号：JPH0332137A
公开(公告)日：1991-02-12
申请号：JP16572189
申请日：1989-06-28
申请人： FUJITSU LTD
发明人： TANAKA HIROKAZU , FUNAKI TETSUJI , UMEDA SADAMI
IPC分类号： H03K5/125 , H03K5/01 , H04L25/02 , H04L25/03
摘要： PURPOSE:To avoid a change in the duty ratio and the effect of a load connecting to the post-stage of the circuit without increase in power consumption and the necessity of a high speed device by transmitting signal corresponding to the duty ratio of the transmission signal in the level edge of the output of a flip-flop circuit. CONSTITUTION:A digital circuit 1 generates signals Q1, and Q1 in response to the level edge of an input signal and they are sent to a reception side via a signal transmission circuit 3, a flip-flop circuit 2 is set by the signal Q1 and reset by signal Q1 and a signal Q2 is outputted. In this case, the signal Q2 rises in coincident with the rising timing of the signal Q1 and falls in coincidence with the rising timing of the signal Q1. Thus, the transmission of the signal Q2 having the same duty rate as that of the input signal being the transmission signal is attained. Thus, the increase in the circuit power consumption and the high speed device are not required and the effect of the load connecting to the post-stage of the circuit is not given on the duty ratio in the digital signal transmission.

10. 发明专利

JPH0292093A SUBSCRIBER CIRCUIT 失效
公开(公告)号：JPH0292093A
公开(公告)日：1990-03-30
申请号：JP24691888
申请日：1988-09-28
申请人： FUJITSU LTD
发明人： FUNAKI TETSUJI , WATAI TAKAHIRO
IPC分类号： H04M19/00 , H04Q3/42 , H04Q3/72
摘要： PURPOSE:To improve detection accuracy by causing a bias current to flow as soon as a loop is started to be closed without causing the bias current to flow in the standby state and increasing/decreasing the bias current in proportion to a detection current. CONSTITUTION:In the case of the standby state, that is, loop current IL=0, no voltage drop across a resistor R1 exists, then detection current IS=0, a bias current of transistors(TRs) 15, 18 is zero, and no current flows to all TRs. When a loop is formed and the loop current IL starts flowing, the detection current IS starts flowing, since the bias current of the TRs 15, 18 change same as the detection current IS flowing to TRs 16, 19, the change in VBE is the same and the detection current IS is accurately proportional to the loop current IL. As a result, the loop detection accuracy is improved.

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