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1. 发明专利

JPS54114134A VARIABLE LENGTH DATA TRANSFER SYSTEM 失效
公开(公告)号：JPS54114134A
公开(公告)日：1979-09-06
申请号：JP2098178
申请日：1978-02-27
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO
发明人： TAKAHASHI HIDEO , YAMADA SHIGEKI , DOI AKIHIKO
IPC分类号： G06F13/12 , G06F3/00 , G06F13/00
摘要： PURPOSE:To omit the renewal working of channel command word CCW with every transmission data block, the emission of the CCW execution indication (SIO order) to DCH and the interruption process work at the end of the data block transfer by making use of the autonomous processing capacity of data channel device DCH. CONSTITUTION:The transmission data of one data block are stored at the data area on memory device MM in the order of transmission. And the transmission byte number m of the transmission data block is stored at the fist lower byte of Pa address. At the same time, CCW showing the transmission order for the stored data is stored at five continuous addresses (Ca-Ca+4). With start by only once SIO order given from central control unit CC, an autonomous renewal is given repetitively for the five continuous CCW by the function of chain command CHC of DCH.

2. 发明专利

JPS52109844A DIAGNOSTIC SYSTEM 失效
公开(公告)号：JPS52109844A
公开(公告)日：1977-09-14
申请号：JP2638476
申请日：1976-03-11
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： KIUCHI YUKIO , KANEDA YOSHIHITO , UCHIDA HIROYASU , DOI AKIHIKO , INAGAKI HIROSHI
IPC分类号： H04Q3/545 , G06F11/00 , G06F11/16 , H04Q3/54
摘要： PURPOSE:To enable approximately the same diagnostic ability as the system using vertification circuit for the diagnose of the faulty central processing unit, by executing the diagnostic program by the normal CPU thru the use of basic and spare temporary memory unit.

3. 发明专利

JPS5226128A REFRESH CONTROL SYSTEM IN STORAGE DEVICE 失效
公开(公告)号：JPS5226128A
公开(公告)日：1977-02-26
申请号：JP10232875
申请日：1975-08-23
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , OKI ELECTRIC IND CO LTD , FUJITSU LTD
发明人： ITOU YOSHITAKA , HONMA YOSHIKAZU , OONISHI NOBORU , DOI AKIHIKO , SHIYOUDA AKIO , MASUNAKA YOSHIHISA , FUJIMATSU TOSHIHIKO
IPC分类号： G11C11/406
摘要： PURPOSE:By judging to receive the refresh request signal from the CPU and storing to display it, the refresh from a plurality of CPUs is made possible and the introduction of an IC memory and the improvement of processing capacity shall be planned.

4. 发明专利

JPS56123168A SIGNAL CIRCUIT TERMINAL CONTROL SYSTEM 失效
公开(公告)号：JPS56123168A
公开(公告)日：1981-09-28
申请号：JP2778080
申请日：1980-03-05
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： TAKAYAMA KATSUNORI , SAITOU ISAO , NAKAMURA YUKIO , DOI AKIHIKO , FUJITA HIROSHI
IPC分类号： H04M7/06 , H04Q3/545 , H04Q11/04
摘要： PURPOSE:To utilize the serial number of a central controller effectively and to improve the processing performance of the central controller, by giving a communication controller two serial numbers and by assigning one to a transmission side and the other to a reception side. CONSTITUTION:Under the control of central controller 6, transmitted data 41, having added signal circuit terminal discrimination information 51, stored in main memory device 41 is sent to communication controller 1. Communication controller 1 stores signal circuit terminal discrimination information 51 in signal circuit terminal information register 22 in common control part 2 to discriminate a signal circuit through which data 41 is to be transmitted and, when it is the 1st signal circuit, transfers data 41 to corresponding signal terminal transmission part 31S in circuit control part 3. Next, data 42 arriving from the 2nd signal circuit is received by signal terminal reception part 32R and at common control part 2, signal circuit terminal information 52 that corresponds to signal terminal reception part 32R is added to received data 42 and stored in receiving buffer 4R.

5. 发明专利

JPS56121138A BUFFER MEMORY CONTROLLING SYSTEM 失效
公开(公告)号：JPS56121138A
公开(公告)日：1981-09-22
申请号：JP2436980
申请日：1980-02-28
申请人： NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： MASUDA ETSUO , NAKAMURA YUKIO , DOI AKIHIKO , FUJITA HIROSHI , HOSOKAWA CHIKAYOSHI
IPC分类号： H04L29/02 , G06F5/06 , G06F7/78 , G06F12/02 , G06F13/00
摘要： PURPOSE:To make it possible to efficiently accomodate and process all kinds of and a lot of different speed circuit terminals, by supervising idle data cells in the buffer area in common and in the lump as to all the circuit terminals, and dynamically controlling the assignment of the idle data cells. CONSTITUTION:After initializing, the data units I37-III39 are inputted from the circuit terminal #i. Data 37-39 are connected with a chain to the idle data cells which have been taken out in order from the idle data cell queue by the input controlling part, and are stored. The data cells 40-42, 43-46, 47-48 correspond to the units I-III, respectively. In this way, a data which has been stored in the buffer area is output to the outside of the memory, after processing. As a result, the data cell becomes idle, is released from the chain connected by the input/output controlling part, and if is added after the end cell of the queue of the idle cell. And, the pointer of the control area is updated by being accompanied by release of the data cell and addition to its idle data cell queue.

6. 发明专利

JPS56110371A COMMUNICATION CONTROLLER 失效
公开(公告)号：JPS56110371A
公开(公告)日：1981-09-01
申请号：JP1238180
申请日：1980-02-06
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO
发明人： NAKAMURA YUKIO , ENDOU TAKENORI , SAITOU ISAO , YAMAUCHI HIDEO , INUI YOSHIO , DOI AKIHIKO
IPC分类号： H04L29/04 , G06F13/00 , H04L12/00 , H04L29/02
摘要： PURPOSE:To realize an application of one communication controller for two systems, by discriminating in correspondence to the lines for several data communication lines having different bit transmission sequence, but, other transmission control procedures are used in common, and then controlling the data communication lines by the bit transmission sequence of each line. CONSTITUTION:The 2-bit register group 61 is provided in correspondence to lines (#0-#N) to store the transmission/reception sequence. The 1st selector 1-SEL selects a register among the group 61 via the selection signal line 401 led from the communication control part CCU plus the output enable signal line 402. The 2nd selector 2-SEL has a structure of m+1 bits and selects the reversed or nonreversed value of the lower-rank bit of the memory address designation line 403 which designates the memory address of the buffer memory BM, and then delivers it as a lower-rank bit of the memory BM. At the same time, the line control part group 62 is provided in correspondence to the lines to perform a control by every line.

7. 发明专利

JPS56108157A DATA PROCESSOR 失效
公开(公告)号：JPS56108157A
公开(公告)日：1981-08-27
申请号：JP881480
申请日：1980-01-30
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： IKUTA AKIRA , MASUDA ETSUO , FUTAGAWA TAKESHI , DOI AKIHIKO , KIMURA AKIO
IPC分类号： G06F12/06 , G06F13/16 , G06F13/28
摘要： PURPOSE:To use an address bus of 8 bits with a CC in common, by isolating successively a 16-bit address given from the DMAC-LSI into a 8-bit row address and a 8-bit line address each for access. CONSTITUTION:The CC, DMAC-LSI and MM have the common memory address bus AB of 8 bits; and the CC, MM and IOC have the common data bus DB. The 16-bit address information given from the DMAC-LSI is first isolated into a row address of 8 bits by the MUX, and a row access is given to the MM through the AB. Then the address information is isolated into a line address of 8 bits, and an access is given to the MM via the AB. The CC sends the address of 8 bits to the MM via the AB to give the row access and then the line access. Thus the address given from the DAMC-LSI is performed by the address bus common to the CC, and accordingly the hardwares is reduced conveniently.

8. 发明专利

JPS5265630A REFRESH CONTROLL CIRCUIT 失效
公开(公告)号：JPS5265630A
公开(公告)日：1977-05-31
申请号：JP14191975
申请日：1975-11-27
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD
发明人： DOI AKIHIKO , ITOU YOSHITAKA , ENDOU AKIRA
IPC分类号： G11C11/406
摘要： PURPOSE:To make small the case of the memory access operation waiting as whole and to minimize a decline of the processing ability by making to concur the refresh operation with the memory access operation.

9. 发明专利

JPS54115036A CONTROL SYSTEM FOR MICROPROGRAM 失效
公开(公告)号：JPS54115036A
公开(公告)日：1979-09-07
申请号：JP2341778
申请日：1978-02-28
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： INUI YOSHIO , DOI AKIHIKO , AMADA HIROYUKI , YAMAUCHI EIOU
IPC分类号： G06F9/22 , G06F3/00 , G06F13/00 , G06F13/38 , G11C7/00
摘要： PURPOSE:To increase the processing ability, by constituting the system that the control processing to perform the data delivery to the line terminal unit and the data write-in operation to the buffer memory is made one machine cycle. CONSTITUTION:The data from the data channel unit DCH is inputted to the input and output data buffer 200. The logical operation section 201 makes the address on the buffer memory 203 to store the said data in one machine cycle. In the next one machine cycle, the logical operation secion 201 takes the reception data from the buffer 200 and inputs it to the data buffer 204. The buffer mrmory 203 stores the content to the designated address in the next machine cycle. In case of data delivery, the logical operation section 201 reads out data from the buffer memory, performs logical operation and the result is inputted to the data buffer. The line contol secion 205 initiates transmission in the next machine cycle. When the delivery operation is executed independently of the microprogram, the transmission can be made by one machine cycle.

10. 发明专利

JPS54115038A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS54115038A
公开(公告)日：1979-09-07
申请号：JP2342078
申请日：1978-02-28
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： DOI AKIHIKO , OOKAWA KAZUMASA , YAMADA SHIGEKI , AMADA HIROYUKI
IPC分类号： G06F9/48
摘要： PURPOSE:To execute service in the order of processing reguest taken place and to perform it econimically, by providing the processing request register, display register after request and the detection circuit for disagreement of the both. CONSTITUTION:The peripheral sections 1,2 producing the processing request in arbitrary time are connected to the processing registration register 4 and the processing request registration register via the bus 9. When the peripheral section 1 requests serive to the control section 7, the processing request register is made by +1 via the operation circuit 6, and the service content of the peripheral section requested is stored in the memory address of the memory 3. On the other hand, the control section 7 detects the disagreement between the processing request registration register 4 and the processing display register 5, and if the exclusive logical sum is other than 0, the serivce is assumed to be present, and the register 5 is made by +1 via the operation circuit 6, the reslt of advance is addressed and accessed to the memory 3, and processing is executed to the peripheral section 1. Thus, the processing request is periodically received and it is sequentially executed.

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