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1. 发明授权

US07554361B2 Level shifter and method thereof 有权
标题翻译：电平移位器及其方法
公开(公告)号：US07554361B2
公开(公告)日：2009-06-30
申请号：US11175415
申请日：2005-07-07
申请人： Nyun-Tae Kim , Ki-Hong Kim
发明人： Nyun-Tae Kim , Ki-Hong Kim
IPC分类号： H03K19/0175
CPC分类号： H03K19/01721 , H03K17/08122 , H03K19/00315 , H03K19/018521
摘要： A level shifter and method thereof. The level shifter may include a protective circuit configured to receive an input signal having an input voltage level, the input signal received on an input line, the protective circuit reducing the input voltage level to generate a stabilized input signal and a first inverter configured to invert the stabilized input signal and to output an inverted output signal at an inverted output voltage level to a first node. In an example method, an input signal may be received at an input voltage level, the input voltage level may be reduced to output a stabilized input signal, the stabilized input signal may be inverted to output an inverted output signal at an inverted output voltage level to a first node and the first node may be transitioned to a node voltage level based on the input signal. The level shifter and method thereof may reduce a power consumption and/or a chip size of a semiconductor device.
摘要翻译：一种电平转换器及其方法。电平移位器可以包括保护电路，其被配置为接收具有输入电压电平的输入信号，在输入线上接收的输入信号，保护电路降低输入电压电平以产生稳定的输入信号，以及配置为反转的第一反相器稳定的输入信号，并将反相输出电压电平的反相输出信号输出到第一节点。在示例性方法中，可以在输入电压电平处接收输入信号，可以减小输入电压电平以输出稳定的输入信号，稳定的输入信号可被反相以在反相的输出电压电平输出反相的输出信号到第一节点，并且第一节点可以基于输入信号被转换到节点电压电平。电平移位器及其方法可以降低半导体器件的功耗和/或芯片尺寸。

2. 发明申请

US20060008041A1 Circuits and methods for recovering a clock signal 有权
标题翻译：用于恢复时钟信号的电路和方法
公开(公告)号：US20060008041A1
公开(公告)日：2006-01-12
申请号：US11172976
申请日：2005-07-05
申请人： Nyun-Tae Kim , Ki-Hong Kim , Kimio Ueda , Shu-Jiang Wang , Mi-Jeong Kim
发明人： Nyun-Tae Kim , Ki-Hong Kim , Kimio Ueda , Shu-Jiang Wang , Mi-Jeong Kim
IPC分类号： H04L25/00
CPC分类号： H04L7/0338 , H03L7/0812 , H04L7/0025
摘要： A circuit for recovering a clock signal may include a frequency multiplier configured to generate a plurality of local clock signals, each having a different phase, based on a plurality of received global clock signals at a first frequency and each having a different phase. The local clock signals may be generated at a second frequency higher than the first frequency. The circuit may include a phase interpolator configured to generate a recovered clock signal at a given phase and at a third frequency, based on the generated local clock signals, and a phase shifter configured to adjust the phase of the recovered clock signal so as to synchronize the phase of the recovered clock signal with a phrase of input data that is input to the phase shifter.
摘要翻译：用于恢复时钟信号的电路可以包括频率乘法器，其被配置为基于多个接收的具有第一频率并且各自具有不同相位的全局时钟信号来产生每个具有不同相位的本地时钟信号。本地时钟信号可以以比第一频率高的第二频率产生。电路可以包括相位插值器，其被配置为基于产生的本地时钟信号在给定相位和第三频率处产生恢复的时钟信号;以及移相器，被配置为调整恢复的时钟信号的相位以便同步恢复的时钟信号的相位与输入到移相器的输入数据的短语。

3. 发明授权

US07656984B2 Circuits and methods for recovering a clock signal 有权
标题翻译：用于恢复时钟信号的电路和方法
公开(公告)号：US07656984B2
公开(公告)日：2010-02-02
申请号：US11172976
申请日：2005-07-05
申请人： Nyun-Tae Kim , Ki-Hong Kim , Kimio Ueda , Shu-Jiang Wang , Mi-Jeong Kim
发明人： Nyun-Tae Kim , Ki-Hong Kim , Kimio Ueda , Shu-Jiang Wang , Mi-Jeong Kim
IPC分类号： H03D3/24
CPC分类号： H04L7/0338 , H03L7/0812 , H04L7/0025
摘要： A circuit for recovering a clock signal may include a frequency multiplier configured to generate a plurality of local clock signals, each having a different phase, based on a plurality of received global clock signals at a first frequency and each having a different phase. The local clock signals may be generated at a second frequency higher than the first frequency. The circuit may include a phase interpolator configured to generate a recovered clock signal at a given phase and at a third frequency, based on the generated local clock signals, and a phase shifter configured to adjust the phase of the recovered clock signal so as to synchronize the phase of the recovered clock signal with a phrase of input data that is input to the phase shifter.
摘要翻译：用于恢复时钟信号的电路可以包括频率乘法器，其被配置为基于多个接收的具有第一频率并且各自具有不同相位的全局时钟信号来产生每个具有不同相位的本地时钟信号。本地时钟信号可以以比第一频率高的第二频率产生。电路可以包括相位插值器，其被配置为基于产生的本地时钟信号在给定相位和第三频率处产生恢复的时钟信号;以及移相器，被配置为调整恢复的时钟信号的相位以便同步恢复的时钟信号的相位与输入到移相器的输入数据的短语。

4. 发明申请

US20060012396A1 Level shifter and method thereof 有权
公开(公告)号：US20060012396A1
公开(公告)日：2006-01-19
申请号：US11175415
申请日：2005-07-07
申请人： Nyun-Tae Kim , Ki-Hong Kim
发明人： Nyun-Tae Kim , Ki-Hong Kim
IPC分类号： H03K19/0175
CPC分类号： H03K19/01721 , H03K17/08122 , H03K19/00315 , H03K19/018521
摘要： A level shifter and method thereof. The level shifter may include a protective circuit configured to receive an input signal having an input voltage level, the input signal received on an input line, the protective circuit reducing the input voltage level to generate a stabilized input signal and a first inverter configured to invert the stabilized input signal and to output an inverted output signal at an inverted output voltage level to a first node. In an example method, an input signal may be received at an input voltage level, the input voltage level may be reduced to output a stabilized input signal, the stabilized input signal may be inverted to output an inverted output signal at an inverted output voltage level to a first node and the first node may be transitioned to a node voltage level based on the input signal. The level shifter and method thereof may reduce a power consumption and/or a chip size of a semiconductor device.

5. 发明申请

US20060018417A1 Phase detection circuit and method thereof and clock recovery circuit and method thereof 有权
标题翻译：相位检测电路及其方法和时钟恢复电路及其方法
公开(公告)号：US20060018417A1
公开(公告)日：2006-01-26
申请号：US11185825
申请日：2005-07-21
申请人： Dae-Seung Jeong , Ki-Mio Ueda , Duck Chang , Hwa-Su Koh , Young-Gyu Kang , Shu-Jiang Wang , Soon-Bok Jang , Nyun-Tae Kim
发明人： Dae-Seung Jeong , Ki-Mio Ueda , Duck Chang , Hwa-Su Koh , Young-Gyu Kang , Shu-Jiang Wang , Soon-Bok Jang , Nyun-Tae Kim
IPC分类号： H03D3/22
CPC分类号： H03L7/091 , H04L7/033
摘要： The phase detection circuit may allow an operating speed of a semiconductor circuit to be increased irrespective of whether a combinational logic circuit within the semiconductor circuit operates at lower operating speeds. The phase detection circuit may adjust a data rate of an input data signal and selectively enable reference signals and error signals. The phase detection circuit may be included within a clock data recovery circuit.
摘要翻译：相位检测电路可以允许半导体电路的操作速度增加，而不管半导体电路内的组合逻辑电路是否以较低的操作速度操作。相位检测电路可以调整输入数据信号的数据速率并选择性地启用参考信号和误差信号。相位检测电路可以包括在时钟数据恢复电路内。

6. 发明申请

US20050017758A1 Method of detecting phase difference, phase detector for performing the same and clock-and-data recovering device including the phase detector 失效
标题翻译：检测相位差的方法，用于执行相位的相位检测器和包括相位检测器的时钟和数据恢复装置
公开(公告)号：US20050017758A1
公开(公告)日：2005-01-27
申请号：US10850162
申请日：2004-05-21
申请人： Nyun-Tae Kim
发明人： Nyun-Tae Kim
IPC分类号： H03L7/085 , H03D13/00
CPC分类号： H03D13/003
摘要： First and fourth phase difference signals, and first and second phase difference information signals respectively having first, fourth, second and third phase differences may be generated using an input signal and a plurality of clock signals each of which has different phase with each other. A level of the first phase difference information signal may be lowered, and a second phase difference signal having a first level less than levels of the first and fourth phase difference signals may be generated. A level of the second phase difference information signal may be lowered, and a third phase difference signal having a second level less than the levels of the first and fourth phase difference signals may be generated. The level of the phase difference signals having a phase difference lower than 45° may be lowered, and thus the operational speed of a CDR device may be maintained and/or the jitter characteristics may be enhanced.
摘要翻译：分别具有第一，第四，第二和第三相位差的第一和第四相位差信号以及第一和第二相位差信息信号可以使用输入信号和多个彼此具有不同相位的时钟信号来产生。可以降低第一相位差信息信号的电平，并且可以产生具有小于第一和第四相位差信号的电平的第一电平的第二相位差信号。可以降低第二相位差信息信号的电平，并且可以产生具有小于第一和第四相位差信号的电平的第二电平的第三相位差信号。具有低于45°的相位差的相位差信号的电平可能降低，因此可以维持CDR设备的操作速度和/或可以提高抖动特性。

7. 发明授权

US07760030B2 Phase detection circuit and method thereof and clock recovery circuit and method thereof 有权
标题翻译：相位检测电路及其方法和时钟恢复电路及其方法
公开(公告)号：US07760030B2
公开(公告)日：2010-07-20
申请号：US11185825
申请日：2005-07-21
申请人： Dae-Seung Jeong , Ki-Mio Ueda , Duck Hyun Chang , Hwa-Su Koh , Young-Gyu Kang , Shu-Jiang Wang , Soon-Bok Jang , Nyun-Tae Kim
发明人： Dae-Seung Jeong , Ki-Mio Ueda , Duck Hyun Chang , Hwa-Su Koh , Young-Gyu Kang , Shu-Jiang Wang , Soon-Bok Jang , Nyun-Tae Kim
IPC分类号： H03L7/00
CPC分类号： H03L7/091 , H04L7/033
摘要： The phase detection circuit may allow an operating speed of a semiconductor circuit to be increased irrespective of whether a combinational logic circuit within the semiconductor circuit operates at lower operating speeds. The phase detection circuit may adjust a data rate of an input data signal and selectively enable reference signals and error signals. The phase detection circuit may be included within a clock data recovery circuit.
摘要翻译：相位检测电路可以允许半导体电路的操作速度增加，而不管半导体电路内的组合逻辑电路是否以较低的操作速度操作。相位检测电路可以调整输入数据信号的数据速率并选择性地启用参考信号和误差信号。相位检测电路可以包括在时钟数据恢复电路内。

8. 发明授权

US07078938B2 Method of detecting phase difference, phase detector for performing the same and clock-and-data recovering device including the phase detector 失效
标题翻译：检测相位差的方法，用于执行相位的相位检测器和包括相位检测器的时钟和数据恢复装置
公开(公告)号：US07078938B2
公开(公告)日：2006-07-18
申请号：US10850162
申请日：2004-05-21
申请人： Nyun-Tae Kim
发明人： Nyun-Tae Kim
IPC分类号： G01R29/00
CPC分类号： H03D13/003
摘要： First and fourth phase difference signals, and first and second phase difference information signals respectively having first, fourth, second and third phase differences may be generated using an input signal and a plurality of clock signals each of which has different phase with each other. A level of the first phase difference information signal may be lowered, and a second phase difference signal having a first level less than levels of the first and fourth phase difference signals may be generated. A level of the second phase difference information signal may be lowered, and a third phase difference signal having a second level less than the levels of the first and fourth phase difference signals may be generated. The level of the phase difference signals having a phase difference lower than 45° may be lowered, and thus the operational speed of a CDR device may be maintained and/or the jitter characteristics may be enhanced.
摘要翻译：分别具有第一，第四，第二和第三相位差的第一和第四相位差信号以及第一和第二相位差信息信号可以使用输入信号和多个彼此具有不同相位的时钟信号来产生。可以降低第一相位差信息信号的电平，并且可以产生具有小于第一和第四相位差信号的电平的第一电平的第二相位差信号。可以降低第二相位差信息信号的电平，并且可以产生具有小于第一和第四相位差信号的电平的第二电平的第三相位差信号。具有低于45°的相位差的相位差信号的电平可能降低，因此可以维持CDR设备的操作速度和/或可以提高抖动特性。

9. 发明授权

US07580491B2 Quarter-rate clock recovery circuit and clock recovering method using the same 有权
标题翻译：四分之一速率时钟恢复电路和使用其的时钟恢复方法
公开(公告)号：US07580491B2
公开(公告)日：2009-08-25
申请号：US11193329
申请日：2005-08-01
申请人： Nyun-Tae Kim , Ki-Mio Ueda , Hwa-Su Koh , Dae-Seung Jeong
发明人： Nyun-Tae Kim , Ki-Mio Ueda , Hwa-Su Koh , Dae-Seung Jeong
IPC分类号： H04L7/00
CPC分类号： H03L7/0814 , H04L7/0025 , H04L7/033
摘要： A quarter-rate clock recovery circuit includes a clock generator, a phase interpolation unit, a phase detector, and a controller. The clock generator generates first through fourth clocks having a quarter frequency of a data-rate of input data, the second, third and fourth clocks have phase differences of 90, 180, and 270 degrees with respect to a phase of the first clock, respectively. The phase interpolation unit performs a phase interpolation on the first through fourth clocks based on control signals to generate fifth through eighth clocks that have a quarter frequency of the data-rate of the input data, the fifth clock tracking a phase of the input data, the sixth, seventh, and eighth clocks respectively have phase differences of 45, 90, and 135 degree with respect to a phase of the fifth clock. The phase detector outputs signals corresponding to phase differences between the input data and the fifth through eighth clocks based on the input data and the fifth through eighth clocks. The controller generates the control signals to control the phase interpolation unit based on the signals output from the phase detector.
摘要翻译：四分之一速率时钟恢复电路包括时钟发生器，相位插值单元，相位检测器和控制器。时钟发生器产生具有输入数据的数据速率的四分之一频率的第一至第四时钟，第二，第三和第四时钟分别相对于第一时钟的相位具有90度，180度和270度的相位差。相位插值单元基于控制信号对第一至第四时钟进行相位插值，以产生具有输入数据的数据速率的四分之一频率的第五至第八时钟，第五时钟跟踪输入数据的相位，第六，第七和第八时钟分别相对于第五时钟的相位具有45度，90度和135度的相位差。相位检测器基于输入数据和第五到第八时钟输出与输入数据和第五至第八时钟之间的相位差相对应的信号。控制器基于从相位检测器输出的信号产生控制信号以控制相位插值单元。

10. 发明申请

US20080042748A1 DB-LINEAR VARIABLE VOLTAGE GAIN AMPLIFIER 审中-公开
标题翻译： DB线性可变电压增益放大器
公开(公告)号：US20080042748A1
公开(公告)日：2008-02-21
申请号：US11782720
申请日：2007-07-25
申请人： Nyun-Tae Kim , Jong-Jae Ruy
发明人： Nyun-Tae Kim , Jong-Jae Ruy
IPC分类号： H03G1/00
CPC分类号： H03G7/06 , H03G1/0029
摘要： A variable voltage gain amplifier in an automatic voltage gain control circuit includes a denominator current source that generates a denominator current corresponding to a denominator a numerator current source that generates a numerator current corresponding to a numerator, and a differential amplifier that amplifies an input voltage with a variable voltage gain and generates an output voltage that is substantially dB-linear with the input voltage when the variable voltage gain that is expressed as an exponential function of a control voltage is approximated to a fraction where each of a denominator and a numerator is expressed as a third order polynomial function of the control voltage.
摘要翻译：自动电压增益控制电路中的可变电压增益放大器包括分母电流源，该分母电流源产生对应于分母的分母电流，分母电流源产生与分子对应的分子电流;以及差分放大器，其放大输入电压与可变电压增益，并且当将表示为控制电压的指数函数的可变电压增益近似为分母和分子表示的分数时，产生与输入电压基本上dB线性的输出电压作为控制电压的三阶多项式函数。

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