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1. 发明授权

US06979810B2 Optical modules and methods of making the optical modules 失效
标题翻译：光模块及其制造方法
公开(公告)号：US06979810B2
公开(公告)日：2005-12-27
申请号：US09930806
申请日：2001-08-15
申请人： Norio Chujo , Keiichi Yamamoto , Akio Osaki , Katsunori Hirano , Takayuki Nakao , Tomoaki Shimotsu , Atsushi Hasegawa , Tetsuya Aoki , Takeshi Yamashita
发明人： Norio Chujo , Keiichi Yamamoto , Akio Osaki , Katsunori Hirano , Takayuki Nakao , Tomoaki Shimotsu , Atsushi Hasegawa , Tetsuya Aoki , Takeshi Yamashita
IPC分类号： H01L31/10 , H01L31/107 , H03L7/085 , H03L7/091 , H04B10/07 , H04B10/2507 , H04B10/40 , H04B10/50 , H04B10/60 , H04L7/033 , H01J40/14 , H03D3/24 , H04B10/06
CPC分类号： H04L7/033 , H03L7/091
摘要： A sample & hold type phase detector is used in a CDR IC and, in jitter transfer bandwidth adjustment, VCO output waveforms 90° out of phase with each other can be inputted to the phase detector, whereby a jitter transfer bandwidth can be calculated by only the measurement of frequency and of a DC voltage and it is possible to make a jitter transfer bandwidth adjustment in DC test for IC.
摘要翻译：在CDR IC中使用采样保持型相位检测器，并且在抖动传输带宽调整中，彼此相位差90°的VCO输出波形可以被输入到相位检测器，由此抖动传输带宽可以仅通过频率和直流电压的测量，可以在IC的直流测试中进行抖动传输带宽调整。

2. 发明授权

US06829441B2 Driver circuit and optical-transmission module 失效
标题翻译：驱动电路和光传输模块
公开(公告)号：US06829441B2
公开(公告)日：2004-12-07
申请号：US10455411
申请日：2003-06-06
申请人： Norio Chujo , Yoshihiko Hayashi , Akio Osaki , Naohiko Baba
发明人： Norio Chujo , Yoshihiko Hayashi , Akio Osaki , Naohiko Baba
IPC分类号： H04B1004
CPC分类号： H04L25/0282 , H04B10/504 , H04B10/564
摘要： A driver circuit comprises a first differential-amplifier circuit having a pair of first transistors with emitters thereof connected to each other and a first resistor provided between an emitter connection point of the first transistors and a first power supply. Different electric potentials are applied to the bases of the pair of the first transistors to set a ratio of a current flowing through one of the pair of the first transistors to a current flowing through the other first transistor at about 1/100 or smaller. An amplitude of an output current is controlled by the higher of the electric potentials applied to the base of one of the first transistors.
摘要翻译：驱动器电路包括具有一对第一晶体管的第一差分放大器电路，其中发射极彼此连接，第一电阻器设置在第一晶体管的发射极连接点与第一电源之间。不同的电位被施加到一对第一晶体管的基极，以将流过一对第一晶体管中的电流的电流与流过另一个第一晶体管的电流的比率约为1/100或更小。输出电流的幅度由施加到第一晶体管之一的基极的较高电位来控制。

3. 发明授权

US06606177B1 Driver circuit and optical-transmission module 失效
公开(公告)号：US06606177B1
公开(公告)日：2003-08-12
申请号：US09392566
申请日：1999-09-09
申请人： Norio Chujo , Yoshihiko Hayashi , Akio Osaki , Naohiko Baba
发明人： Norio Chujo , Yoshihiko Hayashi , Akio Osaki , Naohiko Baba
IPC分类号： H04B1004
CPC分类号： H04L25/0282 , H04B10/504 , H04B10/564
摘要： A driver circuit comprises a first differential-amplifier circuit having a pair of first transistors with emitters thereof connected to each other and a first resistor provided between an emitter connection point of the first transistors and a first power supply. Different electric potentials are applied to the bases of the pair of the first transistors to set a ratio of a current flowing through one of the pair of the first transistors to a current flowing through the other first transistor at about {fraction (1/100)} or smaller. An amplitude of an output current is controlled by the higher of the electric potentials applied to the base of one of the first transistors.

4. 发明授权

US5541553A Amplifier with a function for switching on and off the output signal 失效
标题翻译：具有打开和关闭输出信号功能的放大器
公开(公告)号：US5541553A
公开(公告)日：1996-07-30
申请号：US398678
申请日：1995-03-06
申请人： Norio Chujo , Yoshihiko Hayashi , Akio Osaki
发明人： Norio Chujo , Yoshihiko Hayashi , Akio Osaki
IPC分类号： G01R31/28 , G01R31/319 , H03F1/52 , H03F3/72 , H03K17/615 , H03K17/687 , H03F3/04 , G01R31/02
CPC分类号： H03K17/687 , H03F1/52 , H03F3/72 , H03K17/615
摘要： An amplifier which performs the function of switching on and off its output signal includes an inverted Darlington circuit made up of an input transistor and an output transistor, a first switching circuit connected across the base and the emitter of the output transistor, and a second switching circuit connected between the emitter of the input transistor and the collector of the output transistor. Amplifier also includes means for opening the first switching circuit and closing the second switching circuit to send out an output signal, and for closing the first switching circuit and opening the second switching circuit to stop the output signal. The input and output transistors may be fabricated using vipolar or MOSFET technology because current of a small magnitude flows through the switching circuits, the switching circuits can be formed from elements that are small in size and which have small parasitic capacitance. Consequently, amplifier is capable of operating at high speeds but with low power demands. In addition, amplifier can be miniaturized or formed on a single IC chip.
摘要翻译：执行打开和关闭其输出信号的功能的放大器包括由输入晶体管和输出晶体管组成的反向达林顿电路，连接在输出晶体管的基极和发射极之间的第一开关电路，以及第二开关连接在输入晶体管的发射极和输出晶体管的集电极之间的电路。放大器还包括用于打开第一开关电路并闭合第二开关电路以输出输出信号的装置，并且用于闭合第一开关电路并打开第二开关电路以停止输出信号。输入和输出晶体管可以使用vipolar或MOSFET技术制造，因为小幅度的电流流过开关电路，开关电路可以由尺寸小且具有小寄生电容的元件形成。因此，放大器能够以高速度运行但具有低功率需求。此外，放大器可以在单个IC芯片上小型化或形成。

5. 发明申请

US20090179666A1 OUTPUT BUFFER CIRCUIT, DIFFERENTIAL OUTPUT BUFFER CIRCUIT, OUTPUT BUFFER CIRCUIT HAVING REGULATION CIRCUIT AND REGULATION FUNCTION, AND TRANSMISSION METHOD 有权
标题翻译：输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路及传输方式
公开(公告)号：US20090179666A1
公开(公告)日：2009-07-16
申请号：US12343521
申请日：2008-12-24
申请人： Norio Chujo , Keiichi Yamamoto , Hisaaki Kanai , Toru Yazaki
发明人： Norio Chujo , Keiichi Yamamoto , Hisaaki Kanai , Toru Yazaki
IPC分类号： H03K19/003 , H03K19/0175
CPC分类号： H04L25/0278 , H04L25/028
摘要： An output buffer circuit, a differential output buffer circuit, an output buffer circuit having a regulation circuit and a regulation function, and a transmission method, capable of improving resolution of a pre-emphasis amount without increasing power consumption or a circuit area, in which the output buffer circuit 10 has a function which includes a delay circuit 23, an inverter 22 and output buffers 3 to 7 to transmit a logical signal to a transmission line 2 and generate a waveform having four or more types of signal voltages on a transmission side according to a signal attenuation amount of the transmission line 2 and the output buffer 3 has a variable resistance portion 12 at an on-resistance to change a pre-emphasis amount according to a change in a variable resistance value. The output buffer 3 has a selector 20 on a forward stage and a variable resistance portion 12 at an on-resistance. The inverter 22 is configured to select a signal to be input into the output buffer 6 according to a selector logic, invert a data signal and adjust a tap pre-emphasis amount by a select signal of the selector logic.
摘要翻译：输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路以及传输方法，能够提高预加重量的分辨率而不增加功耗或电路面积，其中输出缓冲电路10具有包括延迟电路23，反相器22和输出缓冲器3〜7的功能，以将逻辑信号发送到传输线2，并在发送侧产生具有四种或更多种信号电压的波形根据传输线2的信号衰减量，输出缓冲器3具有导通电阻的可变电阻部分12，以根据可变电阻值的变化改变预加重量。输出缓冲器3具有前级上的选择器20和导通电阻的可变电阻部分12。反相器22被配置为根据选择器逻辑选择要输入到输出缓冲器6的信号，反转数据信号，并通过选择器逻辑的选择信号来调整抽头预加重量。

6. 发明申请

US20090085688A1 Semiconductor Circuit, and Computing Device and Communications Device Using the Same 有权
标题翻译：半导体电路和使用其的计算设备和通信设备
公开(公告)号：US20090085688A1
公开(公告)日：2009-04-02
申请号：US12145829
申请日：2008-06-25
申请人： Keiichi YAMAMOTO , Norio Chujo , Toru Yazaki , Hisaaki Kanai
发明人： Keiichi YAMAMOTO , Norio Chujo , Toru Yazaki , Hisaaki Kanai
IPC分类号： H03H11/30
CPC分类号： H03F3/3028 , H01L2924/19051 , H03F1/308 , H03F2200/447 , H03F2200/453 , H03K19/017581
摘要： In a semiconductor circuit, an impedance adjustment circuit having the characteristics same as those of a circuit having the nonlinear resistance characteristics is configured to include an operating point calculation circuit automatically calculating an operating point with a reference resistance through feedback control, and an impedance calculation circuit calculating the impedance at the operating point found by the operating point calculation circuit. The impedance adjustment circuit is also provided with an impedance determination circuit that determines whether or not the impedance found by the impedance calculation circuit is in a predetermined range. These components, i.e., the operating point calculation circuit, the impedance calculation circuit, and the impedance determination circuit, are provided each two for High-side and Low-side impedance adjustment use.
摘要翻译：在半导体电路中，具有与具有非线性电阻特性的电路相同特性的阻抗调整电路被配置为包括工作点计算电路，通过反馈控制自动计算具有参考电阻的工作点，以及阻抗计算电路计算由工作点计算电路找到的工作点处的阻抗。阻抗调整电路还设置有阻抗确定电路，其确定由阻抗计算电路发现的阻抗是否在预定范围内。这两个部件，即工作点计算电路，阻抗计算电路和阻抗确定电路，每两个用于高侧和低侧阻抗调节。

7. 发明授权

US07969751B2 High-speed signal transmission apparatus 有权
标题翻译：高速信号传输装置
公开(公告)号：US07969751B2
公开(公告)日：2011-06-28
申请号：US12216737
申请日：2008-07-10
申请人： Keiichi Yamamoto , Norio Chujo , Takashi Kumakura , Yosuke Ishimatsu
发明人： Keiichi Yamamoto , Norio Chujo , Takashi Kumakura , Yosuke Ishimatsu
IPC分类号： H02B1/26
CPC分类号： H05K7/1458 , G06F1/185
摘要： A high-speed signal transmission apparatus comprises: a housing; a plurality of daughter boards juxtaposed to one another in the housing; board-side connectors each provided on corresponding each of the juxtaposed daughter boards; and cable-side connectors fixed in the housing; wherein each of the board-side connectors is insertable/removable into/from corresponding each of the cable-side connectors, and wherein a cable group whose impedance matching can be achieved makes connection between the predetermined cable-side connectors.
摘要翻译：高速信号传输装置包括：壳体; 多个子板在壳体中彼此并置; 每个并置的子板上设置的板侧连接器; 和固定在壳体中的电缆侧连接器; 其中每个电路板侧连接器可插入/移除相应的每个电缆侧连接器，并且其中可实现阻抗匹配的电缆组在预定电缆侧连接器之间进行连接。

8. 发明申请

US20080036512A1 SIGNAL DELAY CIRCUIT AND DRIVER CIRCUIT, SIGNAL TRANSMISSION MODULE, AND SIGNAL TRANSMISSION SYSTEM USING SIGNAL DELAY CIRCUIT 审中-公开
标题翻译：使用信号延迟电路的信号延迟电路和驱动电路，信号传输模块和信号传输系统
公开(公告)号：US20080036512A1
公开(公告)日：2008-02-14
申请号：US11834714
申请日：2007-08-07
申请人： Keiichi Yamamoto , Norio Chujo
发明人： Keiichi Yamamoto , Norio Chujo
IPC分类号： H03K5/14 , H03H11/26 , H03K3/03
CPC分类号： H03H11/265 , H03K5/133 , H03K2005/0013
摘要： A signal delay circuit includes: a first inverter circuit; a second inverter circuit connected to an output terminal of the first inverter; and a feedback circuit extending from an output terminal of the second inverter to its input terminal. A delay time of the first inverter circuit is adjusted by controlling the amount of feedback through the feedback circuit. Here, the feedback circuit is formed by MOS transistors and the delay time is adjusted by controlling the gate voltages of the MOS transistors. The feedback amount is adjusted in relation to a variation in a power supply voltage and a variation in the delay time of the signal delay circuit is suppressed.
摘要翻译：信号延迟电路包括：第一反相器电路; 连接到第一反相器的输出端的第二反相器电路; 以及从第二反相器的输出端子延伸到其输入端子的反馈电路。通过控制通过反馈电路的反馈量来调节第一反相器电路的延迟时间。这里，反馈电路由MOS晶体管形成，并且通过控制MOS晶体管的栅极电压来调整延迟时间。相对于电源电压的变化来调整反馈量，抑制了信号延迟电路的延迟时间的变化。

9. 发明授权

US07902860B2 Semiconductor circuit, and computing device and communications device using the same 有权
标题翻译：半导体电路，以及使用它的计算设备和通信设备
公开(公告)号：US07902860B2
公开(公告)日：2011-03-08
申请号：US12145829
申请日：2008-06-25
申请人： Keiichi Yamamoto , Norio Chujo , Toru Yazaki , Hisaaki Kanai
发明人： Keiichi Yamamoto , Norio Chujo , Toru Yazaki , Hisaaki Kanai
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03F3/3028 , H01L2924/19051 , H03F1/308 , H03F2200/447 , H03F2200/453 , H03K19/017581
摘要： In a semiconductor circuit, an impedance adjustment circuit having the characteristics same as those of a circuit having the nonlinear resistance characteristics is configured to include an operating point calculation circuit automatically calculating an operating point with a reference resistance through feedback control, and an impedance calculation circuit calculating the impedance at the operating point found by the operating point calculation circuit. The impedance adjustment circuit is also provided with an impedance determination circuit that determines whether or not the impedance found by the impedance calculation circuit is in a predetermined range. These components, i.e., the operating point calculation circuit, the impedance calculation circuit, and the impedance determination circuit, are provided each two for High-side and Low-side impedance adjustment use.
摘要翻译：在半导体电路中，具有与具有非线性电阻特性的电路相同特性的阻抗调整电路被配置为包括工作点计算电路，通过反馈控制自动计算具有参考电阻的工作点，以及阻抗计算电路计算由工作点计算电路找到的工作点处的阻抗。阻抗调整电路还设置有阻抗确定电路，其确定由阻抗计算电路发现的阻抗是否在预定范围内。这两个部件，即工作点计算电路，阻抗计算电路和阻抗确定电路，每两个用于高侧和低侧阻抗调节。

10. 发明授权

US07772877B2 Output buffer circuit, differential output buffer circuit, output buffer circuit having regulation circuit and regulation function, and transmission method 有权
标题翻译：输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路及传输方式
公开(公告)号：US07772877B2
公开(公告)日：2010-08-10
申请号：US12343521
申请日：2008-12-24
申请人： Norio Chujo , Keiichi Yamamoto , Hisaaki Kanai , Toru Yazaki
发明人： Norio Chujo , Keiichi Yamamoto , Hisaaki Kanai , Toru Yazaki
IPC分类号： H03K19/003
CPC分类号： H04L25/0278 , H04L25/028
摘要： An output buffer circuit, a differential output buffer circuit, an output buffer circuit having a regulation circuit and a regulation function, and a transmission method, to improve resolution of a pre-emphasis amount without increasing power consumption or a circuit area. The output buffer includes a delay circuit, an inverter and output buffers to transmit a logical signal to a transmission line and generate a waveform having four or more types of signal voltages on a transmission side according to a signal attenuation amount of the transmission line. The output buffer has a selector and a variable resistance portion at an output resistance to change a pre-emphasis amount according to a change in a variable resistance value. The inverter is configured to select a signal to input into the output buffer, invert a data signal and adjust a tap pre-emphasis amount by a select signal of the selector logic.
摘要翻译：输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路以及传输方法，以提高预加重量的分辨率，而不增加功耗或电路面积。输出缓冲器包括延迟电路，反相器和输出缓冲器，以将逻辑信号传输到传输线，并根据传输线的信号衰减量产生在发送侧具有四种或更多种类型的信号电压的波形。输出缓冲器具有输出电阻的选择器和可变电阻部分，以根据可变电阻值的变化改变预加重量。逆变器被配置为选择要输入到输出缓冲器的信号，反转数据信号并通过选择器逻辑的选择信号调整抽头预加重量。

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