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1. 发明授权

US06750541B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06750541B2
公开(公告)日：2004-06-15
申请号：US10127418
申请日：2002-04-23
申请人： Nobuyuki Ohtsuka , Noriyoshi Shimizu , Hisaya Sakai , Yoshiyuki Nakao , Hiroki Kondo , Takashi Suzuki
发明人： Nobuyuki Ohtsuka , Noriyoshi Shimizu , Hisaya Sakai , Yoshiyuki Nakao , Hiroki Kondo , Takashi Suzuki
IPC分类号： H01L2348
CPC分类号： H01L21/76849 , H01L21/76807 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76855 , H01L21/76858 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a multi-layered wiring structure containing a copper layer, comprises a first insulating film formed over a semiconductor substrate, a first copper pattern buried in the first insulating film, a cap layer formed on the first copper pattern and the first insulating film and made of a substance a portion of which formed on the first copper pattern has a smaller electrical resistance value than a portion formed on the first insulating film, second insulating films formed on the cap layer, and a second copper pattern buried in a hole or a trench, which is formed in the second insulating films on the first copper pattern, and connected electrically to the first copper pattern via the cap layer.
摘要翻译：一种具有包含铜层的多层布线结构的半导体器件，包括形成在半导体衬底上的第一绝缘膜，埋在第一绝缘膜中的第一铜图案，形成在第一铜图案上的帽层和第一绝缘层由形成在第一铜图案上的部分的物质制成的薄膜比形成在第一绝缘膜上的部分的电阻值小，形成在盖层上的第二绝缘膜和埋在孔中的第二铜图案或沟槽，其形成在第一铜图案上的第二绝缘膜中，并经由盖层与第一铜图案电连接。

2. 发明授权

US06992005B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US06992005B2
公开(公告)日：2006-01-31
申请号：US10819231
申请日：2004-04-07
申请人： Nobuyuki Ohtsuka , Noriyoshi Shimizu , Hisaya Sakai , Yoshiyuki Nakao , Hiroki Kondo , Takashi Suzuki
发明人： Nobuyuki Ohtsuka , Noriyoshi Shimizu , Hisaya Sakai , Yoshiyuki Nakao , Hiroki Kondo , Takashi Suzuki
IPC分类号： H01L29/72
CPC分类号： H01L21/76849 , H01L21/76807 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76855 , H01L21/76858 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a multi-layered wiring structure containing a copper layer, comprises a first insulating film formed over a semiconductor substrate, a first copper pattern buried in the first insulating film, a cap layer formed on the first copper pattern and the first insulating film and made of a substance a portion of which formed on the first copper pattern has a smaller electrical resistance value than a portion formed on the first insulating film, second insulating films formed on the cap layer, and a second copper pattern buried in a hole or a trench, which is formed in the second insulating films on the first copper pattern; and connected electrically to the first copper pattern via the cap layer.
摘要翻译：一种具有包含铜层的多层布线结构的半导体器件，包括形成在半导体衬底上的第一绝缘膜，埋在第一绝缘膜中的第一铜图案，形成在第一铜图案上的帽层和第一绝缘层由形成在第一铜图案上的部分的物质制成的薄膜比形成在第一绝缘膜上的部分的电阻值小，形成在盖层上的第二绝缘膜和埋在孔中的第二铜图案或形成在第一铜图案上的第二绝缘膜中的沟槽; 并且经由盖层与第一铜图案电连接。

3. 发明授权

US07935624B2 Fabrication method of semiconductor device having a barrier layer containing Mn 有权
标题翻译：具有含有Mn的阻挡层的半导体器件的制造方法
公开(公告)号：US07935624B2
公开(公告)日：2011-05-03
申请号：US11654688
申请日：2007-01-18
申请人： Nobuyuki Ohtsuka , Noriyoshi Shimizu , Yoshiyuki Nakao , Hisaya Sakai
发明人： Nobuyuki Ohtsuka , Noriyoshi Shimizu , Yoshiyuki Nakao , Hisaya Sakai
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76831 , H01L21/76844 , H01L21/76864 , H01L21/76867 , H01L21/76873 , H01L21/76877
摘要： A method for fabricating a semiconductor device includes the steps of forming an opening defined by an inner wall surface in an insulation film, forming a Cu—Mn alloy layer in the opening, depositing a Cu layer on the Cu—Mn alloy layer and filling the opening with the Cu layer, and forming a barrier layer as a result of reaction between Mn atoms in the Cu—Mn alloy layer and the insulation film, wherein the step of forming the barrier layer is conducted by exposing the Cu layer to an ambient that forms a gaseous reaction product when reacted with Mn.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在绝缘膜中形成由内壁表面限定的开口，在开口中形成Cu-Mn合金层，在Cu-Mn合金层上沉积Cu层并填充与Cu层开口，并且由于Cu-Mn合金层中的Mn原子与绝缘膜之间的反应而形成阻挡层，其中形成阻挡层的步骤是通过将Cu层暴露于当与Mn反应时形成气态反应产物。

4. 发明申请

US20070173055A1 Fabrication method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20070173055A1
公开(公告)日：2007-07-26
申请号：US11654688
申请日：2007-01-18
申请人： Nobuyuki Ohtsuka , Noriyoshi Shimizu , Yoshiyuki Nakao , Hisaya Sakai
发明人： Nobuyuki Ohtsuka , Noriyoshi Shimizu , Yoshiyuki Nakao , Hisaya Sakai
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76831 , H01L21/76844 , H01L21/76864 , H01L21/76867 , H01L21/76873 , H01L21/76877
摘要： A method for fabricating a semiconductor device includes the steps of forming an opening defined by an inner wall surface in an insulation film, forming a Cu—Mn alloy layer in the opening, depositing a Cu layer on the Cu—Mn alloy layer and filling the opening with the Cu layer, and forming a barrier layer as a result of reaction between Mn atoms in the Cu—Mn alloy layer and the insulation film, wherein the step of forming the barrier layer is conducted by exposing the Cu layer to an ambient that forms a gaseous reaction product when reacted with Mn.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在绝缘膜中形成由内壁表面限定的开口，在开口中形成Cu-Mn合金层，在Cu-Mn合金层上沉积Cu层并填充与Cu层开口，并且由于Cu-Mn合金层中的Mn原子与绝缘膜之间的反应而形成阻挡层，其中形成阻挡层的步骤是通过将Cu层暴露于环境温度当与Mn反应时形成气态反应产物。

5. 发明授权

US08101513B2 Manufacture method for semiconductor device using damascene method 有权
标题翻译：使用镶嵌法制造半导体器件的方法
公开(公告)号：US08101513B2
公开(公告)日：2012-01-24
申请号：US11366511
申请日：2006-03-03
申请人： Tsuyoshi Kanki , Nobuyuki Ohtsuka , Hisaya Sakai , Noriyoshi Shimizu
发明人： Tsuyoshi Kanki , Nobuyuki Ohtsuka , Hisaya Sakai , Noriyoshi Shimizu
IPC分类号： H01L21/44
CPC分类号： H01L21/3105 , H01L21/02063 , H01L21/76807 , H01L21/76814 , H01L21/76825 , H01L21/76828
摘要： (a) A recess is formed through an insulating film formed over a semiconductor substrate. (b) After the recess is formed, a temperature of the substrate is raised to 300° C. or higher at a temperature rising rate of 10° C./s or slower and a first degassing process is executed. (c) After the first degassing process, a conductive film is deposited on the insulating film, the conductive film being embedded in the recess. (d) The deposited conductive film is polished until the insulating film is exposed. It is possible to suppress occurrence of defects during CMP to be performed after a conductive member is deposited on the surface of the insulating film having a recess formed therethrough.
摘要翻译：（a）通过在半导体衬底上形成的绝缘膜形成凹部。（b）在形成凹部之后，以10℃/秒以下的升温速度将基板的温度升高至300℃以上，进行第一脱气处理。（c）在第一脱气处理之后，在绝缘膜上沉积导电膜，导电膜嵌入凹部中。（d）抛光沉积的导电膜直至暴露绝缘膜。在导电构件沉积在具有通过其形成的凹部的绝缘膜的表面上之后，可以抑制在CMP期间发生的缺陷。

6. 发明授权

US06900542B2 Semiconductor device having increased adhesion between a barrier layer for preventing copper diffusion and a conductive layer, and method of manufacturing the same 有权
标题翻译：具有增加用于防止铜扩散的阻挡层与导电层之间的附着力的半导体器件及其制造方法
公开(公告)号：US06900542B2
公开(公告)日：2005-05-31
申请号：US10428208
申请日：2003-05-02
申请人： Hisaya Sakai , Noriyoshi Shimizu , Nobuyuki Ohtsuka
发明人： Hisaya Sakai , Noriyoshi Shimizu , Nobuyuki Ohtsuka
IPC分类号： H01L21/768 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76846 , H01L21/76858 , H01L21/76867 , H01L21/76873 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises of an insulating film (14) formed over a semiconductor substrate (1), a trench (14b) and a hole (14a) formed in the insulating film (14), a first underlying layer (16) formed in at least one of the trench (14b) and the hole (14a) and made of conductive material to prevent diffusion of copper, a main conductive layer (19) formed in at least one of the trench (14b) and the hole (14a) on the first underlying layer (19) and made of copper or copper alloy, and a second underlying layer (17) formed between the main conductive layer (19) and the first underlying layer (16) and having a metal element that is solid-solved in the main conductive layer at an interface between the second underlying layer (17) and the main conductive layer (19), and formed on the first underlying layer (16) by a CVD method.
摘要翻译：半导体器件包括形成在半导体衬底（1）上的绝缘膜（14），形成在绝缘膜（14）中的沟槽（14b）和孔（14a）），形成第一下层（16）在所述沟槽（14b）和所述孔（14a）中的至少一个中并且由导电材料制成以防止铜的扩散，形成在所述沟槽（14b）中的至少一个中的主导电层（19）和在第一下层（19）上的由铜或铜合金制成的孔（14a）和形成在主导电层（19）和第一下层（16）之间的第二下层（17），并且具有金属元件，其在第二下层（17）和主导电层（19）之间的界面处固溶在主导电层中，并通过CVD法形成在第一下层（16）上。

7. 发明申请

US20070134899A1 Manufacture method for semiconductor device using damascene method 有权
标题翻译：使用镶嵌法制造半导体器件的方法
公开(公告)号：US20070134899A1
公开(公告)日：2007-06-14
申请号：US11366511
申请日：2006-03-03
申请人： Tsuyoshi Kanki , Nobuyuki Ohtsuka , Hisaya Sakai , Noriyoshi Shimizu
发明人： Tsuyoshi Kanki , Nobuyuki Ohtsuka , Hisaya Sakai , Noriyoshi Shimizu
IPC分类号： H01L21/44
CPC分类号： H01L21/3105 , H01L21/02063 , H01L21/76807 , H01L21/76814 , H01L21/76825 , H01L21/76828
摘要： (a) A recess is formed through an insulating film formed over a semiconductor substrate. (b) After the recess is formed, a temperature of the substrate is raised to 300° C. or higher at a temperature rising rate of 10° C./s or slower and a first degassing process is executed. (c) After the first degassing process, a conductive film is deposited on the insulating film, the conductive film being embedded in the recess. (d) The deposited conductive film is polished until the insulating film is exposed. It is possible to suppress occurrence of defects during CMP to be performed after a conductive member is deposited on the surface of the insulating film having a recess formed therethrough.
摘要翻译：（a）通过在半导体衬底上形成的绝缘膜形成凹部。（b）在形成凹部之后，以10℃/秒以下的升温速度将基板的温度升高至300℃以上，进行第一脱气处理。（c）在第一脱气处理之后，在绝缘膜上沉积导电膜，导电膜嵌入凹部中。（d）抛光沉积的导电膜直至暴露绝缘膜。在导电构件沉积在具有通过其形成的凹部的绝缘膜的表面上之后，可以抑制在CMP期间发生的缺陷。

8. 发明授权

US07994055B2 Method of manufacturing semiconductor apparatus, and semiconductor apparatus 有权
标题翻译：制造半导体装置的方法和半导体装置
公开(公告)号：US07994055B2
公开(公告)日：2011-08-09
申请号：US12022742
申请日：2008-01-30
申请人： Hisaya Sakai , Noriyoshi Shimizu
发明人： Hisaya Sakai , Noriyoshi Shimizu
IPC分类号： H01L21/44
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76831 , H01L21/76855 , H01L21/76864 , H01L21/76865 , H01L21/76873
摘要： A method of manufacturing a semiconductor apparatus which includes the steps of forming a via hole and a wire trench reaching an underlying wire in an interlayer insulation film formed on the underlying wire, forming an diffusion barrier film on said underlying wire exposed through said via hole, on an inner wall of said via hole and on an inner wall of said wire trench, forming a seed layer on said underlying wire and on said diffusion barrier film formed on the inner wall of said via hole and the inner wall of said wire trench while concurrently said diffusion barrier film deposited on the bottom of said via hole is being etched, and forming metal wire in said via hole and in said wire trench.
摘要翻译：一种制造半导体装置的方法，包括以下步骤：在形成在下面的导线上的层间绝缘膜中形成到达下层导线的通孔和导线沟槽，在通过所述通孔暴露的所述下层导线上形成扩散阻挡膜，在所述通孔的内壁上和所述导线沟槽的内壁上，在所述底层导线上形成种子层，以及形成在所述通孔的内壁和所述导线沟槽的内壁上的所述扩散阻挡膜上，同时沉积在所述通孔的底部上的所述扩散阻挡膜同时被蚀刻，并且在所述通孔中和所述导线沟槽中形成金属线。

9. 发明申请

US20110021020A1 SEMICONDUCTOR DEVICE AND FABRICATION PROCESS THEREOF 审中-公开
标题翻译：半导体器件及其制造工艺
公开(公告)号：US20110021020A1
公开(公告)日：2011-01-27
申请号：US12895002
申请日：2010-09-30
申请人： Hisaya Sakai , Noriyoshi Shimizu
发明人： Hisaya Sakai , Noriyoshi Shimizu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/2855 , H01L21/76805 , H01L21/76814 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first interconnection pattern embedded in a first insulation film, a second insulation film covering the first interconnection pattern over the first insulation film, an interconnection trench formed in an upper part of the second insulation film, a via-hole extending downward from the interconnection trench at a lower part of the second insulation film, the via-hole exposing the first interconnection pattern, a second interconnection pattern filling the interconnection trench, a via-plug extending downward in the via-hole from the second interconnection pattern and making a contact with the first interconnection pattern, and a barrier metal film formed between the second interconnection pattern and the interconnection trench, the barrier metal film covering a surface of the via-plug continuously, wherein the via-plug has a tip end part invading into the first interconnection pattern across a surface of said first interconnection pattern, the interconnection trench has a flat bottom surface, and the barrier metal film has a larger film thickness at the tip end part of the via-plug as compared with a sidewall surface of the via-plug.
摘要翻译：半导体器件包括嵌入第一绝缘膜中的第一互连图案，覆盖第一绝缘膜上的第一互连图案的第二绝缘膜，形成在第二绝缘膜的上部的互连沟槽，向下延伸的通孔从所述第二绝缘膜的下部的所述互连沟槽，暴露所述第一互连图案的通孔，填充所述互连沟槽的第二互连图案，从所述第二互连图案在所述通孔中向下延伸的通孔插塞;以及与所述第一互连图案接触，以及形成在所述第二互连图案和所述互连沟槽之间的阻挡金属膜，所述阻挡金属膜连续地覆盖所述通孔的表面，其中所述通孔插塞具有尖端部分侵入跨越所述第一互连图案的表面的第一互连图案，互连所述沟槽具有平坦的底面，与所述通孔的侧壁面相比，所述阻挡金属膜在所述通孔的前端部具有较大的膜厚。

10. 发明授权

US07381643B2 Wiring structure forming method and semiconductor device 有权
标题翻译：接线结构形成方法及半导体器件
公开(公告)号：US07381643B2
公开(公告)日：2008-06-03
申请号：US11407920
申请日：2006-04-21
申请人： Hisaya Sakai , Noriyoshi Shimizu
发明人： Hisaya Sakai , Noriyoshi Shimizu
IPC分类号： H01L21/44 , H01L23/52
CPC分类号： H01L21/76843 , H01L21/2855 , H01L21/7684 , H01L21/76865 , H01L21/76873
摘要： After a via hole (102) to connect a lower wiring (101) and an upper wiring not shown is formed in an insulating film (103) using an etching stopper film (104) and a hard mask (105), a base film (106) made from Ta is formed over the insulating film (103) so as to cover an inner wall of the via hole (102) by a one-step low-power bias sputtering method of the present invention. Thus, the base film (106) with a thin and uniform film thickness covering a region from an inner wall surface of the via hole (102) to the insulating film (103) is obtained. This makes it possible to form the base film thin and uniformly over the inner wall surface, that is, from a sidewall surface to a bottom surface, of the opening without causing any disadvantage in terms of wiring formation by relatively simple steps, thereby realizing a highly reliable ultra-fine wiring structure.
摘要翻译：在使用蚀刻停止膜（104）和硬掩模（105）的绝缘膜（103）中形成用于连接下布线（101）和未示出的上布线的通孔（102），基膜 106）形成在绝缘膜（103）上，以便通过本发明的一步低功率偏压溅射法覆盖通孔（102）的内壁。因此，可以获得覆盖从通孔（102）的内壁面到绝缘膜（103）的区域的薄且均匀的薄膜厚度的基膜（106）。这使得可以在开口的内壁表面，即从侧壁表面到底表面上均匀地形成基膜，而不会通过相对简单的步骤在布线形成方面造成任何缺点，从而实现高度可靠的超细线路结构。

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