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1. 发明授权

US5757384A Apparatus and method for font thinning and bolding based upon font outline 失效
标题翻译：基于字体轮廓的字体变薄和加粗的装置和方法
公开(公告)号：US5757384A
公开(公告)日：1998-05-26
申请号：US892832
申请日：1997-07-15
申请人： Nobuyuki Ikeda , Hiroshi Sakurai , Yoshito Kobayashi , Toshinori Otsuka , Hirokazu Yamamoto
发明人： Nobuyuki Ikeda , Hiroshi Sakurai , Yoshito Kobayashi , Toshinori Otsuka , Hirokazu Yamamoto
IPC分类号： G09G5/24 , G06F3/00 , G06K15/02 , G06T5/30 , G06T11/20 , G09G5/28 , G06F3/14
CPC分类号： G06K15/02 , G06T5/30 , G09G5/24 , G09G5/28 , G06K2215/0054 , G09G5/246
摘要： This invention offers a font processor which performs thinning processing, standard processing and bolding processing in outline font according to a resolution level of an output apparatus. According to this invention, a rasterizer generates a raster image in a first area from the outline font, which is stored in a font memory. An outline producer produces an outline image in a second area according to an outline width, which is determined by an outline width determiner. An operation unit makes an logical operation of the raster image and the outline image, and generates an thinned or bolded raster image.
摘要翻译：本发明提供了一种字体处理器，其根据输出设备的分辨率水平执行轮廓字体的稀疏处理，标准处理和加粗处理。根据本发明，光栅化器从存储在字体存储器中的轮廓字体的第一区域中生成光栅图像。轮廓生成器根据由轮廓宽度确定器确定的轮廓宽度在第二区域中产生轮廓图像。操作单元进行光栅图像和轮廓图像的逻辑运算，并生成一个变薄或粗体光栅图像。

2. 发明授权

US5574940A Data processor with quicker latch input timing of valid data 失效
公开(公告)号：US5574940A
公开(公告)日：1996-11-12
申请号：US516317
申请日：1995-08-17
申请人： Toshinori Otsuka
发明人： Toshinori Otsuka
IPC分类号： H03K19/20 , H03K19/003 , H03K19/017 , G06F11/00
CPC分类号： H03K19/00323 , H03K19/01728
摘要： A data processing apparatus includes a first data holding circuit, a second data holding circuit, a signal processing circuit, and a control circuit. The first data holding circuit outputs a signal as three values data representing a first valid value having a first logic value, a second valid value having a second logic value, and an invalid value. The second data holding circuit holds the three values data from the first data holding circuit. The signal processing circuit receives the three values data from the second data holding circuit and outputs a first ready signal indicating completion of data processing. The control circuit controls the second data holding circuit to hold the three values data from the first data holding circuit, and also outputs a second signal indicating completion of data processing in the second data holding circuit to the first data holding circuit when the three values data from the first data holding circuit exhibits one of the first and second valid values and the first ready signal is input from the signal processing circuit.

3. 发明授权

US5471630A Data processor with quicker latch input timing of valid data 失效
标题翻译：数据处理器具有更快的锁存输入定时的有效数据
公开(公告)号：US5471630A
公开(公告)日：1995-11-28
申请号：US143914
申请日：1993-10-27
申请人： Toshinori Otsuka
发明人： Toshinori Otsuka
IPC分类号： H03K19/20 , H03K19/003 , H03K19/017 , G06F11/00
CPC分类号： H03K19/00323 , H03K19/01728
摘要： A data processing apparatus includes a first data holding circuit, a second data holding circuit, a signal processing circuit, and a control circuit. The first data holding circuit outputs a signal as three values data representing a first valid value having a first logic value, a second valid value having a second logic value, and an invalid value. The second data holding circuit holds the three values data from the first data holding circuit. The signal processing circuit receives the three values data from the second data holding circuit and outputs a first ready signal indicating completion of data processing. The control circuit controls the second data holding circuit to hold the three values data from the first data holding circuit, and also outputs a second signal indicating completion of data processing in the second data holding circuit to the first data holding circuit when the three values data from the first data holding circuit exhibits one of the first and second valid values and the first ready signal is input from the signal processing circuit.
摘要翻译：数据处理装置包括第一数据保持电路，第二数据保持电路，信号处理电路和控制电路。第一数据保持电路将信号作为表示具有第一逻辑值的第一有效值，具有第二逻辑值的第二有效值和无效值的三值数据输出。第二数据保持电路保存来自第一数据保持电路的三值数据。信号处理电路从第二数据保持电路接收三值数据，并输出表示数据处理完成的第一就绪信号。控制电路控制第二数据保持电路以保持来自第一数据保持电路的三值数据，并且当三值数据时，第二数据保持电路中指示数据处理完成的第二信号输出到第一数据保持电路从第一数据保持电路显示第一和第二有效值之一，并且从信号处理电路输入第一就绪信号。

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