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1. 发明授权

US06513131B1 Logic circuit having error detection function, redundant resource management method, and fault tolerant system using it 失效
标题翻译：具有错误检测功能的逻辑电路，冗余资源管理方法和使用它的容错系统
公开(公告)号：US06513131B1
公开(公告)日：2003-01-28
申请号：US09376008
申请日：1999-08-19
申请人： Nobuyasu Kanekawa , Shoji Suzuki , Yoshimichi Sato , Korefumi Tashiro , Keisuke Bekki , Hiroshi Sato , Makoto Nohmi , Shinya Ohtsuji
发明人： Nobuyasu Kanekawa , Shoji Suzuki , Yoshimichi Sato , Korefumi Tashiro , Keisuke Bekki , Hiroshi Sato , Makoto Nohmi , Shinya Ohtsuji
IPC分类号： G06F702
CPC分类号： G06F11/0763 , G05B9/03 , G06F11/008 , G06F11/0796 , G06F11/085 , G06F11/1695 , G06F11/18 , G06F11/188 , G06F11/2023 , G06F11/2035 , G06F11/2215
摘要： A self-checking circuit, which is useful for a highly reliable system configuration, includes a logic circuit having an error detection function. For function blocks for feeding out a plurality of signals that are at least duplexed, the logic circuit compares the output signals of the function blocks, and detects an error on the basis of results of the comparison. The logic circuit comprises synthesizing means provided to superimpose inherent waveforms assigned in advance to the respective output signals of the function blocks onto the output signals of one of the function blocks. The inherent waveforms are orthogonal waveforms generated by an orthogonal waveform generator circuit. The logic circuit also comprises comparison means for comparing a signal output of the synthesizing means with the signal output of the other function block to detect an error. The whole circuit including the function blocks are judged normal only if the waveforms inherent to both output signals exist.
摘要翻译：对于高度可靠的系统配置有用的自检电路包括具有错误检测功能的逻辑电路。对于用于输出至少双工的多个信号的功能块，逻辑电路比较功能块的输出信号，并且基于比较的结果来检测错误。逻辑电路包括合成装置，用于将预先分配的固有波形与功能块的各个输出信号叠加到一个功能块的输出信号上。固有波形是由正交波形发生器电路产生的正交波形。逻辑电路还包括比较装置，用于将合成装置的信号输出与另一功能块的信号输出进行比较，以检测误差。包括功能块的整个电路仅在存在两个输出信号固有的波形时才被判断为正常。

2. 发明授权

US6092217A Logic circuit having error detection function, redundant resource management method and fault tolerant system using it 失效
标题翻译：具有错误检测功能的逻辑电路，冗余资源管理方法和使用它的容错系统
公开(公告)号：US6092217A
公开(公告)日：2000-07-18
申请号：US962879
申请日：1997-11-03
申请人： Nobuyasu Kanekawa , Shoji Suzuki , Yoshimichi Sato , Korefumi Tashiro , Keisuke Bekki , Hiroshi Sato , Makoto Nohmi , Shinya Ohtsuji
发明人： Nobuyasu Kanekawa , Shoji Suzuki , Yoshimichi Sato , Korefumi Tashiro , Keisuke Bekki , Hiroshi Sato , Makoto Nohmi , Shinya Ohtsuji
IPC分类号： G05B9/03 , G06F11/00 , G06F11/08 , G06F11/16 , G06F11/18 , G06F11/20 , G06F11/267 , G06F7/02 , H04L1/00
CPC分类号： G06F11/0763 , G05B9/03 , G06F11/085 , G06F11/1695 , G06F11/188 , G06F11/2023 , G06F11/2035 , G06F11/2215 , G06F11/008 , G06F11/0796 , G06F11/18
摘要： A self-checking circuit, which is useful for a highly reliable system configuration, includes a logic circuit having an error detection function. For function blocks for feeding out a plurality of signals that are at least duplexed, the logic circuit compares the output signals of the function blocks, and detects an error on the basis of results of the comparison. The logic circuit comprises synthesizing means provided to superimpose inherent waveforms assigned in advance to the respective output signals of the function blocks onto the output signals of one of the function blocks. The inherent waveforms are orthogonal waveforms generated by an orthogonal waveform generator circuit. The logic circuit also comprises comparison means for comparing a signal output of the synthesizing means with the signal output of the other function block to detect an error. The whole circuit including the function blocks are judged normal only if the waveforms inherent to both output signals exist.
摘要翻译：对于高度可靠的系统配置有用的自检电路包括具有错误检测功能的逻辑电路。对于用于输出至少双工的多个信号的功能块，逻辑电路比较功能块的输出信号，并且基于比较的结果来检测错误。逻辑电路包括合成装置，用于将预先分配的固有波形与功能块的各个输出信号叠加到一个功能块的输出信号上。固有波形是由正交波形发生器电路产生的正交波形。逻辑电路还包括比较装置，用于将合成装置的信号输出与另一功能块的信号输出进行比较，以检测误差。包括功能块的整个电路仅在存在两个输出信号固有的波形时才被判定为正常。

3. 发明授权

US5802266A Logic circuit having error detection function, redundant resource management method, and fault tolerant system using it 失效
标题翻译：具有错误检测功能的逻辑电路，冗余资源管理方法和使用它的容错系统
公开(公告)号：US5802266A
公开(公告)日：1998-09-01
申请号：US323094
申请日：1994-10-14
申请人： Nobuyasu Kanekawa , Shoji Suzuki , Yoshimichi Sato , Korefumi Tashiro , Keisuke Bekki , Hiroshi Sato , Makoto Nohmi , Shinya Ohtsuji
发明人： Nobuyasu Kanekawa , Shoji Suzuki , Yoshimichi Sato , Korefumi Tashiro , Keisuke Bekki , Hiroshi Sato , Makoto Nohmi , Shinya Ohtsuji
IPC分类号： G05B9/03 , G05B13/02 , G06F11/00 , G06F11/08 , G06F11/16 , G06F11/18 , G06F11/20 , G06F11/267 , G06F17/50 , H03K19/007 , G06F7/02 , H04L1/00
CPC分类号： G05B9/03 , G06F11/0763 , G06F11/085 , G06F11/1608 , G06F11/1695 , G06F11/188 , G06F11/2215 , G06F11/0796
摘要： A self-checking circuit, which is useful for a highly reliable system configuration, includes a logic circuit having an error detection function. For function blocks for feeding out a plurality of signals that are at least duplexed, the logic circuit compares the output signals of the function blocks, and detects an error on the basis of results of the comparison. The logic circuit comprises synthesizing circuitry provided to superimpose inherent waveforms assigned in advance to the respective output signals of the function blocks onto the output signals of one of the function blocks. The inherent waveforms are orthogonal waveforms generated by an orthogonal waveform generator circuit. The logic circuit also compares the output signals having the superimposed inherent waveforms with the signal output of the other function block to detect an error. The whole circuit including the function blocks are judged normal only if the waveforms inherent to both output signals exist.
摘要翻译：对于高度可靠的系统配置有用的自检电路包括具有错误检测功能的逻辑电路。对于用于输出至少双工的多个信号的功能块，逻辑电路比较功能块的输出信号，并且基于比较的结果来检测错误。逻辑电路包括合成电路，用于将预先分配的固有波形叠加到功能块的各个输出信号到功能块之一的输出信号上。固有波形是由正交波形发生器电路产生的正交波形。逻辑电路还将具有叠加的固有波形的输出信号与另一功能块的信号输出进行比较，以检测错误。包括功能块的整个电路仅在存在两个输出信号固有的波形时才被判定为正常。

4. 发明授权

US5422965A Air bag operation device 失效
标题翻译：气囊操作装置
公开(公告)号：US5422965A
公开(公告)日：1995-06-06
申请号：US17389
申请日：1993-02-12
申请人： Keisuke Bekki , Hiroshi Sato , Korefumi Tashiro , Seiko Suzuki , Masayoshi Suzuki
发明人： Keisuke Bekki , Hiroshi Sato , Korefumi Tashiro , Seiko Suzuki , Masayoshi Suzuki
IPC分类号： B60R21/16 , B60R21/01 , G01D3/08 , G01P21/00 , B60R21/32
CPC分类号： B60R21/0173 , B60R21/0132 , G01D3/08 , G01P21/00
摘要： An air bag operation device which employs only one CPU module to guarantee sufficient fail-safety in the operation of the air bag without increasing the scale of the hardware. A plurality of crash-discriminating programs of different versions and a plurality of self-diagnosing programs of different versions are executed by a single CPU module, a signal is fed to an air bag igniting device based upon a comparison of the discriminated results by the plurality of crash-discriminating programs, and a signal is fed to an abnormality alarm device based upon comparison of the discriminated results of the plurality of self-diagnosing programs.
摘要翻译：一种安全气囊操作装置，其仅使用一个CPU模块来保证气囊操作中的足够的故障安全性，而不增加硬件的规模。不同版本的多个碰撞鉴别程序和多个不同版本的自诊断程序由单个CPU模块执行，基于多个识别结果的比较将信号馈送到气囊点火装置基于多个自诊断程序的辨别结果的比较，将信号馈送到异常报警装置。

5. 发明授权

US4937755A Production system for an expert system 失效
标题翻译：专家系统的生产系统
公开(公告)号：US4937755A
公开(公告)日：1990-06-26
申请号：US187590
申请日：1988-04-28
申请人： Takayoshi Yokota , Keisuke Bekki , Nobuhiro Hamada
发明人： Takayoshi Yokota , Keisuke Bekki , Nobuhiro Hamada
IPC分类号： G06F9/44 , G06F17/30 , G06F17/50 , G06N5/00 , G06N5/04
CPC分类号： G06N5/046 , G06F17/505 , G06N5/003 , Y10S706/921
摘要： A production system for an expert system comprising: a production rule memory unit storing circuit conversion rules, each having a condition part describing circuit connection and an execution part describing a conversion of the condition part to an equivalent logic circuit dependent upon a predetermined semiconductor technology and further having a provisionally predetermined priority; a task data memory unit storing circuit connection data, each being subjected to an application of the circuit conversion rules; a production rule interpretation and execution unit for selecting a circuit conversion rule in accordance with the provisionally predetermined priority, collating the condition part of the selected circuit conversion rule with the circuit connection data to determine whether the condition part matches with a part of the circuit connection data and, when the both match each other, converting the part of the circuit connection data by the corresponding execution part of the circuit conversion rule to an equivalent logic circuit; further each production rule being provided with a rule flag indicating the collation failure to the circuit connection data, a rule flag memory unit for setting the rule, flag of the circuit conversion rule of which condition part did not match with any of the circuit connection data during the collation cycle, so as to inhibit collation thereafter until collation of all other circuit conversion rules is once completed, thereby increasing the operation speed of the production system for an expert system.

6. 发明授权

US4964056A Automatic design system of logic circuit 失效
标题翻译：逻辑电路自动设计系统
公开(公告)号：US4964056A
公开(公告)日：1990-10-16
申请号：US173251
申请日：1988-03-24
申请人： Keisuke Bekki , Takayoshi Yokota , Tooru Nagai , Nobuhiro Hamada
发明人： Keisuke Bekki , Takayoshi Yokota , Tooru Nagai , Nobuhiro Hamada
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An automatic design system of a logic circuit system includes a storage for storing information about structures and functions of known basic circuits available for a circuit system to be designed, an input device for receiving design specification information about the structures and functions of the circuit to be designed, and a synthesize section for combining the known basic circuits stored in the storage so as to synthesize the desired logic circuit satisfying the design specification information.
摘要翻译：一种逻辑电路系统的自动设计系统，包括存储关于可用于要设计的电路系统的已知基本电路的结构和功能的信息，用于接收关于要被设计的电路的结构和功能的设计规范信息的输入设备以及合成部分，用于组合存储在存储器中的已知基本电路，以便合成满足设计规范信息的所需逻辑电路。

7. 发明授权

US5805134A Method and apparatus of detecting and displaying abnormal conditions utilizing a display control apparatus 失效
标题翻译：利用显示控制装置检测和显示异常情况的方法和装置
公开(公告)号：US5805134A
公开(公告)日：1998-09-08
申请号：US607190
申请日：1996-02-26
申请人： Hiroyuki Seki , Nobuhisa Kobayashi , Keisuke Bekki
发明人： Hiroyuki Seki , Nobuhisa Kobayashi , Keisuke Bekki
IPC分类号： B61L21/00 , B61L25/08 , G06F3/14 , G06F11/00 , G06F11/16 , G08B23/00 , G09G3/04
CPC分类号： G06F11/0796 , B61L21/00 , B61L25/08 , G06F11/162 , G06F3/14 , G06F3/1446
摘要： A highly reliable display control apparatus and method suitable for use in a computer control system which is required to have high degree of reliability, such as control systems for railroad traffic or a nuclear power station. A meaningful symbol is divided into a plurality of sections and these sections are independently input to either one of the inputs of an interactive man-machine system through different systems so that these sections of the meaningful symbol are displayed in the same frame of the man-machine system, thus enabling the operator to visually detect any abnormality as to whether the displayed meaningful symbol is complete or not, whereby a high degree of reliability of the display is obtained.
摘要翻译：适用于需要高度可靠性的计算机控制系统的高度可靠的显示控制装置和方法，例如用于铁路运输的控制系统或核电站。有意义的符号被划分为多个部分，并且这些部分通过不同的系统独立地输入到交互式人机系统的任一输入中，使得有意义符号的这些部分显示在人 - 机器系统，从而使操作者能够可视地检测关于所显示的有意义的符号是否完成的任何异常，从而获得显示的高可靠性。

8. 发明授权

US5065335A Decoding type select logic generating method 失效
标题翻译：解码类型选择逻辑生成方法
公开(公告)号：US5065335A
公开(公告)日：1991-11-12
申请号：US323968
申请日：1989-03-15
申请人： Takayoshi Yokota , Keisuke Bekki , Nobuhiro Hamada
发明人： Takayoshi Yokota , Keisuke Bekki , Nobuhiro Hamada
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A decoding type select logic generating method includes the steps of listing on a group basis input signal names and output destination signal names contained in register transfer descriptions and control codes for commanding execution of the register transfers for each of the same input signal names and same output destination signal names, simplifying logics by replacing the control code having the hamming distance of one by a bit meaning "don't care" on the group basis, generating AND gates for the control codes and the input signal names in each of the groups having the same input signal name and combining the outputs of the AND gates, generating AND gates for the control codes in each group having the same output destination signal name and combining the outputs of the AND gates for each of the output destination signal names, and combining the outputs of the groups each having the same input signal name and the groups each having the same output destination signal name.

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