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1. 发明授权

US06606678B1 Computer system 失效
标题翻译：电脑系统
公开(公告)号：US06606678B1
公开(公告)日：2003-08-12
申请号：US09605399
申请日：2000-06-28
申请人： Nobutaka Nakamura
发明人： Nobutaka Nakamura
IPC分类号： G06F1314
CPC分类号： G06F13/4059
摘要： In this invention, the bus of a computer body is connected to the bus of an expansion unit through a serial interface so as to implement connection wirings in the form of a serial cable. A PCI-PCI bridge for connecting a primary PCI bus to a secondary PCI bus comprises two physically isolated controllers, i.e., a primary PCI serial transfer controller implemented on the PC body side and a secondary PCI serial transfer controller implemented on the docking station side. The two controllers are connected to each other through serial LVDS lines. Transactions are exchanged between the primary PCI bus and the secondary PCI bus by serial transfer between the primary PCI serial transfer controller and the secondary PCI serial transfer controller.
摘要翻译：在本发明中，计算机机身的总线通过串行接口连接到扩展单元的总线，以实现串行电缆形式的连接布线。用于将主PCI总线连接到辅助PCI总线的PCI-PCI桥接器包括两个物理隔离的控制器，即在PC主体侧实现的主PCI串行传输控制器和在对接站侧上实现的辅助PCI串行传输控制器。两个控制器通过串行LVDS线相互连接。通过主PCI串行传输控制器和辅助PCI串行传输控制器之间的串行传输，在主PCI总线和辅助PCI总线之间交换交易。

2. 发明授权

US5280589A Memory access control system for use with a relatively small size data processing system 失效
标题翻译：存储器访问控制系统，用于使用相对较小的数据处理系统
公开(公告)号：US5280589A
公开(公告)日：1994-01-18
申请号：US689720
申请日：1991-04-22
申请人： Nobutaka Nakamura
发明人： Nobutaka Nakamura
IPC分类号： G06F13/28 , G06F1/00
CPC分类号： G06F13/285
摘要： A memory access control system is disclosed. In this system, a CPU, a low speed memory, a high speed memory and direct memory access controller (DMAC) are connected to a system bus. A high speed memory is connected through a local bus to the CPU. A control circuit is connected to the local bus, the system bus and the high speed memory. A bidirectional buffer is connected to the local and system buses. When the CPU accesses the high speed memory, the control circuit addresses the high speed memory and disables the buffer. As a result, data can directly be transferred between the CPU and the high speed memory. When the CPU accesses the low speed memory, the control circuit drives the system bus according to a protocol of the system bus, thereby to address the low speed memory and enables the buffer. As a result, data can be transferred between the CPU and the low speed memory, via a route of the local bus, the buffer and the system bus. When the DMAC accesses the high speed memory, the control circuit addresses the high speed memory and enables the buffer according to the system bus protocol. As a result, data can be transferred between the DMAC and the high speed memory, through a route of the local bus, the buffer, and the system bus. When the DMAC accesses the low speed memory, the control circuit disables the high speed memory and the buffer.
摘要翻译：公开了一种存储器访问控制系统。在该系统中，CPU，低速存储器，高速存储器和直接存储器存取控制器（DMAC）连接到系统总线。高速存储器通过本地总线连接到CPU。控制电路连接到局部总线，系统总线和高速存储器。双向缓冲器连接到本地和系统总线。当CPU访问高速存储器时，控制电路解决高速存储器并禁用缓冲器。因此，可以直接在CPU和高速存储器之间传输数据。当CPU访问低速存储器时，控制电路根据系统总线的协议来驱动系统总线，从而寻址低速存储器并启用缓冲器。因此，可以通过本地总线，缓冲器和系统总线的路由在CPU和低速存储器之间传输数据。当DMAC访问高速存储器时，控制电路解决高速存储器，并根据系统总线协议启用缓冲器。因此，可以通过本地总线，缓冲器和系统总线的路由在DMAC和高速存储器之间传输数据。当DMAC访问低速存储器时，控制电路禁用高速存储器和缓冲器。

3. 发明授权

US4724493A Floppy disk drive interface circuit 失效
标题翻译：软盘驱动器接口电路
公开(公告)号：US4724493A
公开(公告)日：1988-02-09
申请号：US884639
申请日：1986-07-11
申请人： Nobutaka Nakamura
发明人： Nobutaka Nakamura
IPC分类号： G11B20/14 , G06F3/06 , G06F13/00 , G11B5/016 , G11B5/09 , G11B20/10
CPC分类号： G06F3/0601 , G11B20/10 , G11B5/016 , G06F2003/0692
摘要： A floppy disk drive interface circuit of the invention has a counter/selector for counting the pulse width of a window signal supplied from a voltage frequency oscillator. When a window pulse having a pulse width longer or shorter than a preset pulse width is input, counter/selector supplies a disable signal to AND gate 22. AND gate 22blocks window signal 12 from VFO2 being supplied to FDC 3.
摘要翻译：本发明的软盘驱动器接口电路具有用于对从电压频率振荡器提供的窗口信号的脉冲宽度进行计数的计数器/选择器。当输入具有比预设脉冲宽度更长或更短的脉冲宽度的窗口脉冲时，计数器/选择器向与门22提供禁止信号。与门22阻挡来自VFO2的窗口信号12被提供给FDC 3。

4. 发明授权

US06829670B1 Using consecutive block IDs to keep track of data transferred across a serially linked bridge 失效
标题翻译：使用连续块ID来跟踪跨串行链路传输的数据
公开(公告)号：US06829670B1
公开(公告)日：2004-12-07
申请号：US09702755
申请日：2000-11-01
申请人： Nobutaka Nakamura
发明人： Nobutaka Nakamura
IPC分类号： G06F1336
CPC分类号： H04L1/18 , G06F13/4059 , H04L1/16
摘要： A PCI-PCI bridge is composed of two physically different controllers, i.e., a primary PCI serial transfer controller arranged at a PC, and a secondary PCI serial transfer controller arranged at a docking station. In data transfer between these controllers, preliminary transmission of block data having a block ID assigned thereto and a return of ACK having the block ID assigned thereto are performed asynchronously. The transmission party can determine which data item is the last the receiving party has received by employing a block ID assigned to NAK. When NAK is received from the receiving party, re-transmission from a block waiting for NAK is started. In this manner, data required to transmit a bus transaction between buses can be transferred accurately and speedily between two controllers.
摘要翻译： PCI-PCI桥由两个物理上不同的控制器组成，即布置在PC处的主PCI串行传输控制器，以及布置在对接站处的辅助PCI串行传输控制器。在这些控制器之间的数据传输中，异步地执行具有分配给其的块ID的块数据的初始传输和分配给其的具有块ID的ACK的返回。发送方可以通过使用分配给NAK的块ID来确定接收方已经接收到哪个数据项。当从接收方接收到NAK时，从等待NAK的块开始重新发送。以这种方式，可以在两个控制器之间准确且快速地传送在总线之间传送总线事务所需的数据。

5. 发明授权

US06622191B1 Computer system 失效
标题翻译：电脑系统
公开(公告)号：US06622191B1
公开(公告)日：2003-09-16
申请号：US09702990
申请日：2000-11-01
申请人： Nobutaka Nakamura
发明人： Nobutaka Nakamura
IPC分类号： G06F1300
CPC分类号： G06F13/4027
摘要： A PCI-PCI bridge which connects a primary PCI (Peripheral Component Interconnect) bus and a secondary PCI bus comprises two physically different controllers, a primary PCI serial transfer controller located on a PC (Personal Computer) body side and a secondary PCI serial transfer controller located on a docking station side. Both controllers are connected together by serial LVDS (Low Voltage Differential Signal) lines, and data needed to transfer a bus cycle is serially transferred between both controllers. An interrupt signal generated on the docking station side is serially transferred to the primary PCI serial transfer controller from the secondary PCI serial transfer controller via the serial LVDS lines for transferring data in a bus cycle.
摘要翻译：连接主PCI（外围组件互连）总线和辅助PCI总线的PCI-PCI桥接器包括两个物理上不同的控制器，位于PC（个人计算机）主体侧的主PCI串行传输控制器和辅助PCI串行传输控制器位于对接站侧。两个控制器通过串行LVDS（低电压差分信号）线连接在一起，传输总线周期所需的数据在两个控制器之间串行传输。在对接站侧产生的中断信号通过串行LVDS线从副PCI串行传输控制器串行传输到主PCI串行传输控制器，用于在总线周期中传输数据。

6. 发明授权

US06257757B1 Thermal analysis apparatus 失效
标题翻译：热分析仪
公开(公告)号：US06257757B1
公开(公告)日：2001-07-10
申请号：US09313117
申请日：1999-05-17
申请人： Nobutaka Nakamura
发明人： Nobutaka Nakamura
IPC分类号： G01N2500
CPC分类号： G01N25/4846
摘要： A gas-tight container such as a glove box maintains a sample under a controlled atmosphere and has a sample chamber formed in a convex portion thereof. The temperature is controlled in the sample chamber by an externally disposed heater. A detector such as a weight detector is disposed in the gas-tight container and has a sample holder for holding a sample under analysis. The detector is movably supported by a movement mechanism so that the sample holder is movable between a first position at which a sample disposed on the sample holder is disposed within the sample chamber and a second position at which a sample disposed on the sample holder is disposed outside the sample chamber, such that the mounting of a sample on the sample holder may be accomplished while the sample holder is disposed outside the sample chamber and a thermal analysis of the sample may be performed while the sample is disposed inside the sample chamber. Gas inlet and outlet ports are provided to form a stream of purge gas to continually replace the atmosphere in the gas-tight chamber and the sample chamber, and the gas produced by the sample during analysis thereof is discharged together with the purge gas through a gas discharge port provided at a tip of the sample chamber.
摘要翻译：诸如手套箱的气密容器将样品保持在可控气氛下，并且具有形成在其凸部中的样品室。通过外部设置的加热器在样品室中控制温度。诸如重量检测器的检测器设置在气密容器中并且具有用于保持分析中的样品的样品保持器。检测器由移动机构可移动地支撑，使得样品保持器可以在设置在样品室中的样品设置在第一位置和设置在样品架上的样品所在的第二位置之间移动在样品室外部，可以在将样品保持器设置在样品室外部时将样品安装在样品架上，并且可以在将样品置于样品室内部时进行样品的热分析。提供气体入口和出口以形成净化气体流，以持续更换气密室和样品室中的气氛，并且在分析期间由样品产生的气体与吹扫气体一起通过气体排出口设置在样品室的顶端。

7. 发明授权

US6146012A Differential thermal analyzer 有权
标题翻译：差热分析仪
公开(公告)号：US6146012A
公开(公告)日：2000-11-14
申请号：US232472
申请日：1999-01-15
申请人： Nobutaka Nakamura , Rintaro Nakatani , Ryoichi Kinoshita
发明人： Nobutaka Nakamura , Rintaro Nakatani , Ryoichi Kinoshita
IPC分类号： G01N25/00 , G01N25/20 , G01N25/48
CPC分类号： G01N25/4866 , G01N25/4833
摘要： The DSC (DTA) signal waveform measured under an experimental heating rate condition is separated into a base line and individual basic peak elements, and the respective activation energies are calculated corresponding to each of basic peak elements separated. A DSC (DTA) signal that should be obtained at an another heating rate is estimated from the data obtained from the experimental heating rate and it is outputted. In this process, the temperature shift caused by heating rate difference is corrected using the values of activation energies obtained.
摘要翻译：将在实验加热速率条件下测量的DSC（DTA）信号波形分离为基线和各个基本峰值元素，并且相应于分离的每个基本峰值元素计算各自的活化能。根据从实验加热速率获得的数据估计应以另一加热速率获得的DSC（DTA）信号，并输出。在该过程中，使用所获得的活化能的值校正由加热速率差导致的温度偏移。

8. 发明授权

US5901292A Computer system having expansion unit 失效
标题翻译：具有扩展单元的计算机系统
公开(公告)号：US5901292A
公开(公告)日：1999-05-04
申请号：US808414
申请日：1997-02-28
申请人： Nobutaka Nishigaki , Nobutaka Nakamura
发明人： Nobutaka Nishigaki , Nobutaka Nakamura
IPC分类号： G06F1/18 , G06F3/00 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4022
摘要： An analog switch is provided to be connected to the signal lines of a bus of a computer body to be led to an expansion unit. When the signal lines of the bus of the expansion unit are pulled up, a high value is sent to the signal lines of the bus of the computer body. When the signal lines of the bus of the expansion unit are pulled down, a low value is sent to the signal lines of the bus of the computer body. After the potential levels of the signal lines of one bus equal to those of the signal lines of the other bus by the high value or the low value sent, a connection control gate array sets the analog switch on. This can allow the signal lines of both buses to be connected together without causing a transient phenomenon even while the bus cycle is being executed.
摘要翻译：提供模拟开关以连接到要引导到扩展单元的计算机主体的总线的信号线。当扩展单元的总线的信号线被拉起时，高值被发送到计算机机身总线的信号线。当扩展单元的总线的信号线被拉下时，将低值发送到计算机机身总线的信号线。在一个总线的信号线的电位电平等于另一总线的信号线的电平等于高值或低值发送后，连接控制门阵列设置模拟开关。即使在执行总线周期时，也可以使两个总线的信号线连接在一起，而不引起瞬时现象。

9. 发明授权

US5892977A Apparatus and method for read-accessing write-only registers in a DMAC 失效
标题翻译：在DMAC中读取只读寄存器的设备和方法
公开(公告)号：US5892977A
公开(公告)日：1999-04-06
申请号：US694757
申请日：1996-08-09
申请人： Nobutaka Nakamura
发明人： Nobutaka Nakamura
IPC分类号： G06F13/28 , G06F13/10
CPC分类号： G06F13/28
摘要： A computer system has an I/O address space with an ISA bus, and a configuration address space with a PCI bus, further the system including an ISA DMA (Direct Memory Access) controller with two or more DMA channels on the ISA bus, an I/O register implemented in the DMA controller for storing information for DMA transfer on each of the DMA channels, and a register control logic device for controlling read/write-access to the I/O register. The I/O registers are allocated to the I/O address space, and further write-only registers in the I/O registers are allocated to the configuration address space. When a HOST-PCI bridge device generates a configuration read cycle through the configuration address space on the PCI bus, the register control logic device read-accesses the write-only registers, in response to the generated configuration read cycle.
摘要翻译：计算机系统具有具有ISA总线的I / O地址空间和具有PCI总线的配置地址空间，该系统还包括在ISA总线上具有两个或更多DMA通道的ISA DMA（直接存储器访问）控制器，在DMA控制器中实现的I / O寄存器，用于存储每个DMA通道上DMA传输的信息，以及用于控制对I / O寄存器的读/写访问的寄存器控制逻辑器件。 I / O寄存器分配给I / O地址空间，I / O寄存器中的其他只写寄存器分配给配置地址空间。当HOST-PCI桥接器件通过PCI总线上的配置地址空间产生配置读周期时，寄存器控制逻辑器件响应于所生成的配置读周期读访问只写寄存器。

10. 发明授权

US5742849A High-performance computer system of a parallel write-buffering type 失效
标题翻译：并行写缓冲型高性能计算机系统
公开(公告)号：US5742849A
公开(公告)日：1998-04-21
申请号：US796955
申请日：1997-02-07
申请人： Nobutaka Nakamura
发明人： Nobutaka Nakamura
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G06F13/00
CPC分类号： G06F13/1673 , G06F13/4243
摘要： A computer system including a high speed CPU, a low speed main memory, and a system controller which has a write buffer coupled to the processor data bus in parallel to the main memory for latching CPU write data. The system controller includes a gate array LSI, and an address buffer which is coupled to the CPU through a processor address bus and to the main memory through a memory address bus. When the write buffer latches the write data from the CPU, the system controller suspends the transfer of the write data to the main memory before completion of the memory write cycle. The memory write cycle is completed by transferring the latched data in the write buffer to the main memory before the CPU begins the next read/write cycle. This above configuration enables the CPU to operate with increased performance during read/write cycles and since the write buffer is connected to the CPU and main memory in parallel the number of pins required for interfacing the write buffer to the CPU and main memory is reduced compared to a configuration using a serially connected write buffer.
摘要翻译：一种包括高速CPU，低速主存储器和系统控制器的计算机系统，其具有与主存储器并行耦合到处理器数据总线的写入缓冲器，用于锁存CPU写入数据。系统控制器包括门阵列LSI和地址缓冲器，其通过处理器地址总线耦合到CPU，并通过存储器地址总线连接到主存储器。当写入缓冲器锁存来自CPU的写入数据时，系统控制器在完成存储器写入周期之前暂停将写入数据传送到主存储器。在CPU开始下一个读/写周期之前，通过将写缓冲区中的锁存数据传送到主存储器来完成存储器写周期。上述配置使CPU能够在读/写周期期间以更高的性能进行操作，并且由于写入缓冲器并行连接到CPU和主存储器，所以将写入缓冲器与CPU和主存储器连接所需的引脚数量减少了比较使用串行连接的写入缓冲器进行配置。

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