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1. 发明授权

US4967387A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4967387A
公开(公告)日：1990-10-30
申请号：US199605
申请日：1988-05-27
申请人： Nobuo Shibasaki , Toshio Tanaka , Yoshiharu Nagayama , Kenjiro Yasunari
发明人： Nobuo Shibasaki , Toshio Tanaka , Yoshiharu Nagayama , Kenjiro Yasunari
IPC分类号： G06F11/267 , G06F15/78 , G11C29/12 , G11C29/48
CPC分类号： G06F11/2236 , G06F15/7842 , G11C29/12 , G11C29/48
摘要： A microprocessor having a plurality of memories comprises an address selection means which supplies selectively, to the memories, the address signal generated by the address generation means provided in the microprocessor and the test address signal supplied from the external circuit. Thereby, the address of memories can be accessed directly from the external circuit for the test of memories. Moreover, the microprocessor is provided with the test bus through which the signal transmitted between the function blocks in the microprocessor is input or output from or to the external circuit. Accordingly, the function block can be tested easily.
摘要翻译：具有多个存储器的微处理器包括：地址选择装置，用于向存储器选择性地提供由微处理器中提供的地址产生装置产生的地址信号和从外部电路提供的测试地址信号。因此，可以从外部电路直接访问存储器的地址以进行存储器的测试。此外，微处理器设置有测试总线，通过该测试总线在微处理器中的功能块之间传输的信号通过其输入或输出到外部电路。因此，可以容易地测试功能块。

2. 发明授权

US4779084A Apparatus for generating memory address of a display memory 失效
标题翻译：一种用于产生显示存储器的存储器地址的装置
公开(公告)号：US4779084A
公开(公告)日：1988-10-18
申请号：US15015
申请日：1987-02-17
申请人： Toshio Tanaka , Hiroyuki Sakai , Nobuo Shibasaki
发明人： Toshio Tanaka , Hiroyuki Sakai , Nobuo Shibasaki
IPC分类号： G09G5/34 , G06F3/153 , G09G5/40 , G09G1/16
CPC分类号： G09G5/40
摘要： A memory address signal for a display memory is generated from a memory address generating circuit. The memory address generating circuit has an offset register and a memory address counter in addition to a memory address register. The offset register stores an offset value corresponding to a difference between a width of the display memory and a width of a display picture in a scanning direction. The memory address counter counts up a character clock in order to deliver the memory address signal after loading a start address of each horizontal scanning line of the display picture. At the end of each horizontal scanning line, an adder adds the offset value to the memory address signal. The addition thereof is loaded into the address register as the start address of the next horizontal scanning line.
摘要翻译：从存储器地址产生电路产生用于显示存储器的存储器地址信号。存储器地址生成电路除了存储器地址寄存器之外还具有偏移寄存器和存储器地址计数器。偏移寄存器存储对应于显示存储器的宽度和扫描方向上的显示画面的宽度之间的差的偏移值。存储器地址计数器计数字符时钟，以便在加载显示图像的每个水平扫描行的开始地址之后传送存储器地址信号。在每个水平扫描线的末端，加法器将偏移值与存储器地址信号相加。其添加被加载到地址寄存器中作为下一个水平扫描线的起始地址。

3. 发明授权

US5524087A Method of forming a signal wave from first and second waveform data 失效
标题翻译：从第一和第二波形数据形成信号波的方法
公开(公告)号：US5524087A
公开(公告)日：1996-06-04
申请号：US367596
申请日：1995-01-03
申请人： Masanobu Kawamura , Hiroyuki Kida , Seiji Kamada , Toshiyuki Tojo , Takeshi Ohkubo , Hiroyuki Matsuura , Naoki Yashiki , Nobuo Shibasaki
发明人： Masanobu Kawamura , Hiroyuki Kida , Seiji Kamada , Toshiyuki Tojo , Takeshi Ohkubo , Hiroyuki Matsuura , Naoki Yashiki , Nobuo Shibasaki
IPC分类号： H03B28/00 , G06F1/035 , H03K3/78 , H03K4/02 , H03K4/92 , H04L29/10 , G06F1/02
CPC分类号： G06F1/035
摘要： A variable wave forming circuit is provided which produces signals of various waveforms (e.g., sine, triangular or trapezoidal waves) and various frequencies. A random access memory (memory means) 121 to store wave formation information on waveform is provided. According to the wave formation information stored in the memory means, the updating or keeping of a digital value in an increment/decrement circuit 123 is controlled and the digital value is digital/analog-converted by a digital/analog (D/A) conversion circuit 124, which is controlled by a digital value control means that includes the increment/decrement circuit 123. By writing appropriate wave formation information into the memory means, it is possible to produce signals of desired waveforms.
摘要翻译：提供了一种产生各种波形（例如，正弦波，三角波或梯形波）和各种频率的信号的可变波形成电路。提供了存储关于波形的波形信息的随机存取存储器（存储装置）121。根据存储在存储装置中的波形信息，控制增量/减量电路123中的数字值的更新或保持，并且通过数字/模拟（D / A）转换对数字值进行数/模转换电路124由包括增量/递减电路123的数字值控制装置控制。通过将适当的波形形成信息写入存储装置，可以产生所需波形的信号。

4. 发明授权

US06393561B1 Disk drive computer with programmable nonvolatile memory capable of rewriting a control program of the disk drive 失效
标题翻译：具有可编程非易失性存储器的磁盘驱动器计算机，能够重写磁盘驱动器的控制程序
公开(公告)号：US06393561B1
公开(公告)日：2002-05-21
申请号：US09171002
申请日：1999-02-10
申请人： Mitsuo Hagiwara , Hiromasa Takahashi , Satoshi Yamato , Nobuo Shibasaki , Mitsuo Yotsutani , Tsutomu Ishii
发明人： Mitsuo Hagiwara , Hiromasa Takahashi , Satoshi Yamato , Nobuo Shibasaki , Mitsuo Yotsutani , Tsutomu Ishii
IPC分类号： G06F900
CPC分类号： G06F3/0614 , G06F3/0623 , G06F3/0632 , G06F3/0644 , G06F3/0658 , G06F3/0674 , G06F3/0676 , G06F3/0677 , G06F8/65 , G06F9/4401
摘要： A microcomputer (5) which is an integrated circuit including an electrically erasable and programmable nonvolatile semiconductor memory (56) and a central processing unit (51) is used for control of a disk drive (2). The nonvolatile semiconductor memory holds an application program such as a recorded information reproducing control program in an application program area (561), and holds a reboot program used for updating the application program in a reboot program area (560). The central processing unit executes the reboot program to rewrite the application program in whole or part, in response to a rewrite command for the application program which is supplied from the outside.
摘要翻译：作为包括电可擦除可编程非易失性半导体存储器（56）和中央处理单元（51）的集成电路的微型计算机（5）被用于控制盘驱动器（2）。非易失性半导体存储器在应用程序区域（561）中保存诸如记录信息再现控制程序的应用程序，并且将重新启动程序保存在重新启动程序区域（560）中。响应于从外部提供的应用程序的重写命令，中央处理单元执行重新启动程序以全部或部分重写应用程序。

5. 发明授权

US07076649B2 Disk drive and computer 失效
标题翻译：磁盘驱动器和电脑
公开(公告)号：US07076649B2
公开(公告)日：2006-07-11
申请号：US10765170
申请日：2004-01-28
申请人： Mitsuo Hagiwara , Hiromasa Takahashi , Satoshi Yamato , Nobuo Shibasaki , Mitsuo Yotsutani , Tsutomu Ishii
发明人： Mitsuo Hagiwara , Hiromasa Takahashi , Satoshi Yamato , Nobuo Shibasaki , Mitsuo Yotsutani , Tsutomu Ishii
IPC分类号： G06F9/00
CPC分类号： G06F3/0614 , G06F3/0623 , G06F3/0632 , G06F3/0644 , G06F3/0658 , G06F3/0674 , G06F3/0676 , G06F3/0677 , G06F8/65 , G06F9/4401
摘要： A microcomputer which is an integrated circuit including an electrically erasable and programmable nonvolatile semiconductor memory and a central processing unit is used for control of a disk drive. The nonvolatile semiconductor memory holds an application program such as a recorded information reproducing control program in an application program area, and holds a reboot program used for updating the application program in a reboot program area. The central processing unit executes the reboot program to rewrite the application program in whole or part, in response to a rewrite command for the application program which is supplied from the outside.
摘要翻译：作为包括电可擦除和可编程的非易失性半导体存储器和中央处理单元的集成电路的微计算机被用于磁盘驱动器的控制。非易失性半导体存储器在应用程序区域中保存诸如记录信息再现控制程序的应用程序，并且在重新启动程序区域中保存用于更新应用程序的重新启动程序。响应于从外部提供的应用程序的重写命令，中央处理单元执行重新启动程序以全部或部分重写应用程序。

6. 发明授权

US5418734A Finely adjustable signal wave forming circuit including complementary clock signal counters 失效
标题翻译：精细可调信号波形成电路包括互补时钟信号计数器
公开(公告)号：US5418734A
公开(公告)日：1995-05-23
申请号：US80803
申请日：1993-06-21
申请人： Masanobu Kawamura , Hiroyuki Kida , Seiji Kamada , Toshiyuki Tojo , Takeshi Ohkubo , Hiroyuki Matsuura , Naoki Yashiki , Nobuo Shibasaki
发明人： Masanobu Kawamura , Hiroyuki Kida , Seiji Kamada , Toshiyuki Tojo , Takeshi Ohkubo , Hiroyuki Matsuura , Naoki Yashiki , Nobuo Shibasaki
IPC分类号： H03B28/00 , G06F1/035 , H03K3/78 , H03K4/02 , H03K4/92 , H04L29/10 , G06F1/02
CPC分类号： G06F1/035
摘要： A variable wave forming circuit is provided which produces signals of various waveforms (e.g., sine, triangular or trapezoidal waves) and various frequencies. A random access memory (memory means) 121 to store wave formation information on waveform is provided. According to the wave formation information stored in the memory means, the updating or keeping of a digital value in an increment/decrement circuit 123 is controlled and the digital value is digital/analog-converted by a digital/analog (D/A) conversion circuit 124, which is controlled by a digital value control means that includes the increment/decrement circuit 123. By writing appropriate wave formation information into the memory means, it is possible to produce signals of desired waveforms.
摘要翻译：提供了一种产生各种波形（例如，正弦波，三角波或梯形波）和各种频率的信号的可变波形成电路。提供了存储关于波形的波形信息的随机存取存储器（存储装置）121。根据存储在存储装置中的波形信息，控制增量/减量电路123中的数字值的更新或保持，并且通过数字/模拟（D / A）转换对数字值进行数/模转换电路124由包括增量/递减电路123的数字值控制装置控制。通过将适当的波形形成信息写入存储装置，可以产生所需波形的信号。

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