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1. 发明授权

US06741127B2 High-frequency amplifier circuit and radio communication apparatus using same 失效
标题翻译：高频放大器电路和使用它的无线电通信装置
公开(公告)号：US06741127B2
公开(公告)日：2004-05-25
申请号：US10118210
申请日：2002-04-09
申请人： Noboru Sasho , Shigeo Kusunoki , Masayoshi Abe
发明人： Noboru Sasho , Shigeo Kusunoki , Masayoshi Abe
IPC分类号： H03G320
CPC分类号： H03G3/3042 , H03F1/0227 , H03G3/004
摘要： In a high-frequency amplifier circuit, a power detector detects input power, an A/D converter converts the detection output into a digital signal, and then a digital LPF averages the digital signal to obtain data of the average value of input power level. Control data corresponding to the data of the average value is supplied as a control voltage from a DC-to-DC converter controlling memory to a DC-to-DC converter via a D/A means. Thus, a low output voltage vdd is supplied from the DC-to-DC converter to a power amplifier as circuit supply voltage of the power amplifier at the times of medium and low output power to control unnecessary current consumption by the power amplifier and thereby increase efficiency of the power amplifier at the times of medium and low output power.
摘要翻译：在高频放大器电路中，功率检测器检测输入功率，A / D转换器将检测输出转换成数字信号，然后数字LPF对数字信号进行平均以获得输入功率电平的平均值的数据。对应于平均值的数据的控制数据通过D / A装置作为控制电压从DC-DC转换器控制存储器提供给DC-DC转换器。因此，低输出电压Vdd从中间和低输出功率被提供给功率放大器的功率放大器作为功率放大器的电源电压，以控制功率放大器的不必要的电流消耗，从而增加功率放大器在中低输出功率时的效率。

2. 发明授权

US06999528B2 I/Q demodulator device with three power detectors and two A/D converters 失效
标题翻译： I / Q解调器具有三个功率检测器和两个A / D转换器
公开(公告)号：US06999528B2
公开(公告)日：2006-02-14
申请号：US09947145
申请日：2001-09-05
申请人： Veselin Brankovic , Dragan Krupezevic , Mohamed Ratni , Masayoshi Abe , Noboru Sasho
发明人： Veselin Brankovic , Dragan Krupezevic , Mohamed Ratni , Masayoshi Abe , Noboru Sasho
IPC分类号： H03D3/22 , H04L27/22
CPC分类号： H03D1/2245 , H03D3/007 , H03D9/04 , H04B1/30
摘要： The present invention relates to a method and a device for the I/Q demodulation of modulated RF signals. The I/Q demodulator (60) has a first input for the RF signal (61) to be demodulated and a second input for a RF signal (62) originating from a local oscillator (20). The demodulator (60) combines the two RF signals (61,62) to generate three output signals supplied to three power detectors. In a combination unit (70) the three power signals of the power detectors are merged in two signal branches wherein after passing an A/D converting (72) and digital processing unit (73) one signal is the I component and the other one is the Q component of the received modulated RF signal (61).
摘要翻译：本发明涉及用于调制RF信号的I / Q解调的方法和装置。 I / Q解调器（60）具有要被解调的RF信号（61）的第一输入和源自本地振荡器（20）的RF信号（62）的第二输入。解调器（60）组合两个RF信号（61,62）以产生提供给三个功率检测器的三个输出信号。在组合单元（70）中，功率检测器的三个功率信号被合并在两个信号分支中，其中在通过A / D转换（72）和数字处理单元（73）之后，一个信号是I分量，另一个是所接收的调制RF信号（61）的Q分量。

3. 发明申请

US20060284652A1 Power detecting circuit and demodulator comprising it 审中-公开
标题翻译：功率检测电路和解调器组成
公开(公告)号：US20060284652A1
公开(公告)日：2006-12-21
申请号：US10493241
申请日：2001-10-31
申请人： Masayoshi Abe , Noboru Sasho , Dragan Krupezevic , Veselin Brankovic , Mohamed Ratni
发明人： Masayoshi Abe , Noboru Sasho , Dragan Krupezevic , Veselin Brankovic , Mohamed Ratni
IPC分类号： H03K9/06
CPC分类号： H03D1/18
摘要： A high performance power detection circuit suitable to be made monolithic, being compact and low at cost, suitable to a radio-frequency operation in a wide band, having excellent linearity in detection characteristics, small fluctuation of detection characteristics against bias fluctuation, small fluctuation of detection characteristics against FET threshold voltage fluctuation and a small DC offset, which does not require an additional circuit even when a subsequent circuit has a balanced input; and a demodulator using the same. The power detection circuit uses two transistors (FET) Q101 and Q102 having approximately same characteristics, wherein a connection point of sources are connected to a resistor element R103 as a current source, are used as active elements; gates and drains of the transistors Q101 and Q102 are supplied with approximately same bias voltages; drains of them are supplied with approximately same drain bias voltages; a capacitor C104, wherein a capacitance value is set to be a sufficiently large value, is connected between sources of transistors Q101 and Q102 and a ground; capacitors C102 and C103, wherein capacitance values are approximately same and set to be sufficiently large values, are connected between drains of the transistors Q101 and Q102 and a ground; a radio-frequency signal RFin is supplied to a gate of the transistor Q101; and a voltage difference between a drain of the transistor Q101 and a drain of the transistor Q102 is regarded as a detection output.
摘要翻译：高性能功率检测电路适用于单片，小巧，成本低，适用于宽带的射频工作，检测特性线性好，检测特性与偏置波动的波动小，波动小即使在后续电路具有平衡输入的情况下也不需要额外的电路; 以及使用该解调器的解调器。功率检测电路使用具有大致相同特性的两个晶体管（FET）Q 101和Q 102，其中源极的连接点连接到作为电流源的电阻器元件R 103用作有源元件; 晶体管Q 101和Q 102的栅极和漏极被提供有大致相同的偏置电压; 它们的漏极具有大致相同的漏极偏置电压; 将电容值设定为足够大的电容器C 104连接在晶体管Q 101和Q 102的源极与地之间; 电容器C 102和C 103，其中电容值大致相同且设置为足够大的值，连接在晶体管Q 101和Q 102的漏极与地之间; 射频信号RFin被提供给晶体管Q 101的栅极; 将晶体管Q101的漏极与晶体管Q102的漏极之间的电压差作为检测输出。

4. 发明授权

US07039129B2 Demodulator structure utilizing DC switches 失效
标题翻译：采用直流开关的解调器结构
公开(公告)号：US07039129B2
公开(公告)日：2006-05-02
申请号：US09901273
申请日：2001-07-09
申请人： Mohamed Ratni , Dragan Krupezevic , Veselin Brankovic , Masayoshi Abe , Noboru Sasho
发明人： Mohamed Ratni , Dragan Krupezevic , Veselin Brankovic , Masayoshi Abe , Noboru Sasho
IPC分类号： H44L27/16
CPC分类号： H04L27/22 , H03D3/007 , H04B1/30
摘要： The present invention relates to an I/Q demodulator (21) comprising a n-port structure (1,16) is provided, wherein n is an integer value of 4,5 or 6. The demodulator (21) is supplied at a first input (3) with a RF signal (2) which has to be demodulated. At a second input (5) it is supplied with a second RF signal (4). The n−2 output signals (6) are detected by power sensors (7). After low pass filtering (14) the output signals of the power sensors (7) are multiplexed by a multiplexing means (8).
摘要翻译：本发明涉及一种包括n端口结构（I16）的I / Q解调器（21），其中n是4,5或6的整数值。解调器（21）以第一输入（3）与必须被解调的RF信号（2）。在第二输入（5）处，它被提供有第二RF信号（4）。 n-2个输出信号（6）由功率传感器（7）检测。在低通滤波（14）之后，功率传感器（7）的输出信号由复用装置（8）复用。

5. 发明授权

US06823181B1 Universal platform for software defined radio 失效
标题翻译：用于软件定义无线电的通用平台
公开(公告)号：US06823181B1
公开(公告)日：2004-11-23
申请号：US10070283
申请日：2002-07-23
申请人： Ryuji Kohno , Masayoshi Abe , Noboru Sasho , Shinichiro Haruyama , Robert Henry Morelos-Zaragoza , Francis Swarts , Pieter Van Rooyen , Yukitoshi Sanada , Lachlan Bruce Michael , Hamid Amir-Alikhani , Veselin Brankovic
发明人： Ryuji Kohno , Masayoshi Abe , Noboru Sasho , Shinichiro Haruyama , Robert Henry Morelos-Zaragoza , Francis Swarts , Pieter Van Rooyen , Yukitoshi Sanada , Lachlan Bruce Michael , Hamid Amir-Alikhani , Veselin Brankovic
IPC分类号： H04B126
CPC分类号： H04B1/30 , H03D1/2245 , H04L27/2273 , H04L27/2332
摘要： The universal platform for the SDR of the present invention employs the direct conversion approach with the n-port MMIC followed by reconfigurable reprogrammable devices such as DSP's or FPGA's. The universal platform is based on the linear operation of the devices. Thus, the DC offset problem may be solved. It is also possible to support very wide bandwidths compared with conventional I/Q receivers. Therefore, the present universal platform is suitable for multimode and multiband communications.
摘要翻译：本发明的SDR的通用平台采用n端口MMIC的直接转换方法，其次是可重新配置的可编程器件，如DSP或FPGA。通用平台基于设备的线性操作。因此，可以解决DC偏移问题。与传统I / Q接收机相比，也可以支持非常宽的带宽。因此，目前的通用平台适用于多模和多频通信。

6. 发明授权

US06900693B2 Power amplifying apparatus and radio communications apparatus using same 失效
标题翻译：功率放大装置及其使用的无线通信装置
公开(公告)号：US06900693B2
公开(公告)日：2005-05-31
申请号：US10429714
申请日：2003-05-06
申请人： Noboru Sasho , Masayoshi Abe
发明人： Noboru Sasho , Masayoshi Abe
IPC分类号： H03F1/02 , H03F1/32 , H03F3/21 , H04B1/04 , H03G3/30
CPC分类号： H03F1/0266 , H03F1/3223 , H03F3/24 , H04B2001/0441
摘要： By extracting a portion of RF signals from an input side of a multistage RF amplifier with a detector, and converting extracted signals into envelope signals, low-frequency second-harmonic distortion components are efficiently extracted. Then, the extracted low-frequency second-harmonic distortion components are amplified with a low-frequency amplifier, and phase adjusted with a phase shifter, after which they are injected into a gate or base bias of the final stage of the multistage RF amplifier. As a result, the low-frequency second-harmonic distortion components are converted into third-harmonic distortion due to the non-linearity of transistors, and the third-harmonic distortion thus obtained cancels out the third-harmonic distortion originally present in the multistage RF amplifier.
摘要翻译：通过使用检测器从多级RF放大器的输入侧提取一部分RF信号，并将提取的信号转换为包络信号，可以有效地提取低频二次谐波失真分量。然后，提取的低频二次谐波失真分量用低频放大器放大，并用移相器进行相位调整，然后将其注入到多级RF放大器的最后级的栅极或基极偏置中。结果，低频二次谐波失真分量由于晶体管的非线性而被转换为三次谐波失真，并且由此获得的三次谐波失真抵消了原始存在于多级RF中的三次谐波失真放大器

7. 发明授权

US06683471B2 Power detector using FET transistor 失效
标题翻译：功率检测器采用FET晶体管
公开(公告)号：US06683471B2
公开(公告)日：2004-01-27
申请号：US09938146
申请日：2001-08-22
申请人： Mohamed Ratni , Dragan Krupezevic , Veselin Brankovic , Masayoshi Abe , Noboru Sasho
发明人： Mohamed Ratni , Dragan Krupezevic , Veselin Brankovic , Masayoshi Abe , Noboru Sasho
IPC分类号： G01R3126
CPC分类号： G01R21/10
摘要： The present invention relates to a circuitry for detecting the power of a RF signal (7) comprising a FET transistor (1) connected in parallel to two inputs (2, 2′) for supplying the RF signal and two outputs (13, 13′) for detecting the power of the RF signal (7). The circuitry has a resistor (9) having a resistance larger than the drain-source resistance of the FET transistor (1). This resistor (9) is connected between one of the outputs and the source (14) of the FET transistor (19. Further a capacitor (10) is connected between one of the input and the source of the FET transistor. The gate (8) of the FET transistor is connected to ground.
摘要翻译：本发明涉及一种用于检测RF信号（7）的功率的电路，该RF信号（7）包括并联连接到用于提供RF信号的两个输入（2,2'）的FET晶体管（1），以及两个输出（13,13' ），用于检测RF信号（7）的功率。电路具有电阻（9），其电阻大于FET晶体管（1）的漏极 - 源极电阻。该电阻器（9）连接在FET晶体管（19）的一个输出端和源极（14）之间。此外，电容器（10）连接在FET晶体管的输入源和源极之一中，栅极（8））的FET晶体管连接到地。

8. 发明申请

US20050111587A1 Demodulator and receiver using same 审中-公开
标题翻译：解调器和接收器使用相同
公开(公告)号：US20050111587A1
公开(公告)日：2005-05-26
申请号：US10473417
申请日：2001-11-30
申请人： Masayoshi Abe , Noboru Sasho , Dragan Krupezevic , Veselin Brankovic , Mohamed Ratni
发明人： Masayoshi Abe , Noboru Sasho , Dragan Krupezevic , Veselin Brankovic , Mohamed Ratni
IPC分类号： H03D3/00 , H04B1/30 , H04L27/14
CPC分类号： H03D3/007 , H04B1/30
摘要： A high performance demodulator able to realize a further wide band property, low distortion characteristics, and low power consumption in comparison with a conventional multi-port demodulator and having a small fluctuation in characteristics with respect to temperature fluctuations and aging and comprising a five-port junction circuit 101 receiving a received signal Sr and a local signal Slo generated at a local signal generation circuit 102, generating three signals having a phase difference, detecting signal levels (amplitude components) of these signals to obtain three power detection signals (baseband signals) P1, P2, and P3; a first multiplier 103 for multiplying the power detection signal P1 output from a first power detector of the five-port junction circuit 101 by a coefficient A1 (=(κ21/κ11)2) for canceling square components of an interference signal and a local signal; a second multiplier 104 for multiplying the power detection signal P1 output from the first power detector by a coefficient A2 (=(κ31/κ11)2) for canceling square components of an interference signal and a local signal; a first subtractor 105 for subtracting a multiplication result of the first multiplier 103 from the power detection signal P2 output from a second power detector of the five-port junction circuit 101; a second subtractor 106 for subtracting the multiplication result of the second multiplier 104 from the power detection signal P3 output from a third power detector of the five-port junction circuit 101; and a multi-port signal-to-IQ signal conversion circuit 109 for converting the result to an In-phase signal I and a quadrature signal Q as demodulated signals based on the output signals of the first subtractor 105 and the second subtractor 106.
摘要翻译：与传统的多端口解调器相比，能够实现更宽带特性，低失真特性和低功耗的高性能解调器，并且相对于温度波动和老化具有小的特性波动，并且包括五端口接收接收信号Sr和在本地信号发生电路102产生的本地信号Slo，产生具有相位差的三个信号，检测这些信号的信号电平（振幅分量）以获得三个功率检测信号（基带信号） P 1，P 2和P 3; 第一乘法器103，用于将从五端口电路101的第一功率检测器输出的功率检测信号P 1乘以系数A 1（=（kappa 21 / kappa＆lt; / SUB>）^{2），用于消除干扰信号和本地信号的平方分量; 第二乘法器104，用于将从第一功率检测器输出的功率检测信号P 1乘以系数A 2（=（kappa 31 / kappa）11）），用于消除干扰信号和本地信号的平方分量; 第一减法器105，用于从从五端口电路101的第二功率检测器输出的功率检测信号P 2中减去第一乘法器103的相乘结果; 第二减法器106，用于从从五端口电路101的第三功率检测器输出的功率检测信号P 3中减去第二乘法器104的相乘结果; 以及用于将结果转换为基于第一减法器105和第二减法器106的输出信号的解调信号的同相信号I和正交信号Q的多端口信号到IQ信号转换电路109。}

9. 发明授权

US06710716B1 Power detecting circuit and demodulator comprising the same 失效
标题翻译：功率检测器和解调器使用相同
公开(公告)号：US06710716B1
公开(公告)日：2004-03-23
申请号：US10048538
申请日：2002-01-31
申请人： Masayoshi Abe , Noboru Sasho , Dragan Krupezevic , Veselin Brankovic
发明人： Masayoshi Abe , Noboru Sasho , Dragan Krupezevic , Veselin Brankovic
IPC分类号： G08B2100
CPC分类号： H03D1/18
摘要： A high performance power detector not only suited for monolithic structures, small in size, low in cost, and suitabed for broadband high frequency operations, but also excellent in the linearity of the detection characteristic, having a small fluctuation of detection characteristic relative to the bias fluctuation, having a small fluctuation of detection characteristic relative to the FET threshold voltage fluctuation, and in addition having a small DC offset wherein an additional circuit is unnecessary even if the latter stage circuit has a balance input, and a demodulator using the same.
摘要翻译：高性能功率检测器不仅适用于单块结构，尺寸小，成本低，适用于宽带高频操作，而且具有优异的检测特性线性度，相对于偏置具有较小的检测特性波动波动，相对于FET阈值电压波动具有小的检测特性波动，并且另外具有小的DC偏移，其中即使后级电路具有平衡输入也不需要附加电路，以及使用该偏移的解调器。

10. 发明授权

US07974363B2 Receiver, receiving method, filter circuit, and control method 有权
标题翻译：接收机，接收方式，滤波电路及控制方法
公开(公告)号：US07974363B2
公开(公告)日：2011-07-05
申请号：US11869965
申请日：2007-10-10
申请人： Hideki Yokoshima , Masayoshi Abe , Yuya Kondo , Yukitoshi Sanada
发明人： Hideki Yokoshima , Masayoshi Abe , Yuya Kondo , Yukitoshi Sanada
IPC分类号： H03K9/00 , H04L27/00 , H03M1/12 , H03M3/00 , H03M1/66
CPC分类号： H04B1/0021 , H04B1/28
摘要： A receiver supporting a plurality of radio communication systems having different specifications includes a setting unit, a clock generation circuit, a voltage-current conversion amplifier, a switch, integrators, an AD conversion circuit, and a feedback circuit. The setting unit sets a value suitable for a carrier frequency used in one selected radio communication system. The clock generation circuit generates a first clock having a first frequency and a second clock having a second frequency. The conversion amplifier converts an input voltage signal into a current signal. The switch switches between connection and disconnection modes in accordance with the first clock to output the current signal. Each integrator operates in accordance with the second clock and includes two or more switched capacitor circuits and an operational amplifier. The AD conversion circuit converts a signal supplied from the preceding integrator into digital form. The feedback circuit operates in accordance with the second clock.
摘要翻译：支持具有不同规格的多个无线电通信系统的接收机包括设置单元，时钟发生电路，电压 - 电流转换放大器，开关，积分器，AD转换电路和反馈电路。设置单元设置适合于一个所选无线电通信系统中使用的载波频率的值。时钟产生电路产生具有第一频率的第一时钟和具有第二频率的第二时钟。转换放大器将输入电压信号转换为电流信号。该开关根据第一个时钟在连接和断开模式之间切换以输出当前信号。每个积分器根据第二时钟进行操作，并且包括两个或更多个开关电容器电路和运算放大器。 AD转换电路将从前一积分器提供的信号转换为数字形式。反馈电路根据第二时钟进行工作。

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