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1. 发明授权

US07908529B2 Flash memory 有权
标题翻译：闪存
公开(公告)号：US07908529B2
公开(公告)日：2011-03-15
申请号：US12371659
申请日：2009-02-16
申请人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
发明人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
IPC分类号： G11C29/00 , G11C16/04 , H03M13/00
CPC分类号： G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1072 , G11C7/1006 , G11C16/0483 , G11C16/10 , G11C2029/0411 , G11C2207/104
摘要： A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal.
摘要翻译：闪速存储器包括存储器扇区，命令接口，第一信号缓冲器，控制信号生成电路，数据输入缓冲器，纠错电路，地址缓冲器，地址信号生成电路，多个数据存储电路，和写电路。命令接口从外部设备接收写入数据输入指令，生成写入数据输入指令信号，并从外部设备接收写入指令，生成写入指令信号。误差校正电路由写数据输入指令信号激活，以与写使能信号同步地接收写入数据，并由写指令信号激活，以产生与控制信号同步的纠错校验数据。

2. 发明授权

US07894259B2 Nonvolatile semiconductor memory device with first and second write sequences controlled by a command or an address 有权
标题翻译：具有由命令或地址控制的第一和第二写入序列的非易失性半导体存储器件
公开(公告)号：US07894259B2
公开(公告)日：2011-02-22
申请号：US12576638
申请日：2009-10-09
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/3436 , G11C16/3454 , G11C29/70 , G11C29/832 , G11C2211/5621 , G11C2211/5641
摘要： A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.
摘要翻译：存储单元阵列具有第一和第二存储区域。第一存储区具有由地址信号选择的存储元件。第二存储区域具有由控制信号选择的存储元件。控制电路具有熔丝元件。当熔丝元件被熔断时，控制电路在第二存储区域上禁止写入和擦除中的至少一个。

3. 发明授权

US07394695B2 Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells 有权
标题翻译：具有连接到存储单元的位线的多个数据存储部分的非易失性半导体存储器
公开(公告)号：US07394695B2
公开(公告)日：2008-07-01
申请号：US11511488
申请日：2006-08-29
申请人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
发明人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C7/1051 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/12 , G11C16/24 , G11C16/3431 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643 , G11C2211/5649 , G11C2211/565 , G11C2216/14
摘要： Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.
摘要翻译：具有三个以上值的数据以非易失性方式存储在存储单元中。数据电路具有多个存储电路。多个存储电路中的一个是锁存电路。多个存储电路中的另一个是电容器。锁存电路和电容器用于临时存储具有两位或更多位的程序/读数据。如果由于泄漏引起的数据变化导致程序，则使用锁存电路来刷新由电容器保持的数据。结果，即使使用多级数据，数据电路也不会变大。

4. 发明授权

US07164605B2 Semiconductor memory device and electric device with the same 有权
标题翻译：半导体存储器件和电器件相同
公开(公告)号：US07164605B2
公开(公告)日：2007-01-16
申请号：US11305193
申请日：2005-12-19
申请人： Koichi Kawai , Tomoharu Tanaka , Noboru Shibata
发明人： Koichi Kawai , Tomoharu Tanaka , Noboru Shibata
IPC分类号： G11C16/06
CPC分类号： G11C16/3468
摘要： A semiconductor memory device includes: a plurality of cell array blocks in each of which a plurality of memory cells are arranged; address decode circuits for selecting memory cells in the cell array blocks; sense amplifier circuits for reading cell data of the cell array blocks; and a busy signal generation circuit for generating a busy signal to the chip external, wherein in a first read cycle selecting a first area in a first cell array block, cell data read operations for the first area of the first cell array block and a second area of a second cell array block are simultaneously executed, while the busy signal generation circuit generates a true busy signal, and then a read data output operation is executed for outputting the read out data of the first area held in the sense amplifier circuits to the chip external, and in a second read cycle selecting the second area in the second cell array block, after the busy signal generation circuit has output a dummy busy signal shorter in time length than the true busy signal without executing cell data read operation, a read data output operation is executed for outputting the read out data of the second area held in the sense amplifier circuits to the chip external.
摘要翻译：半导体存储器件包括：多个单元阵列块，每个单元阵列块中布置有多个存储单元; 用于选择单元阵列块中的存储单元的地址解码电路; 用于读取单元阵列块的单元数据的读出放大器电路; 以及用于向芯片外部产生忙信号的忙信号产生电路，其中在第一读周期中选择第一单元阵列块中的第一区，对第一单元阵列块的第一区进行单元数据读操作，同时执行第二单元阵列块的区域，而忙信号产生电路产生真正的忙信号，然后执行读数据输出操作，以将保持在读出放大器电路中的第一区域的读出数据输出到芯片外部，并且在第二读取周期中选择第二单元阵列块中的第二区域，在忙信号产生电路在不执行单元数据读取操作的情况下输出比真实忙信号更短的时间长度的虚拟忙信号，读取执行数据输出操作，以将保持在读出放大器电路中的第二区域的读出数据输出到芯片外部。

5. 发明授权

US07120052B2 Semiconductor memory device for storing multivalued data 有权
公开(公告)号：US07120052B2
公开(公告)日：2006-10-10
申请号：US11325917
申请日：2006-01-04
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C11/34
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3459 , G11C2211/5621 , G11C2211/5646 , G11C2211/5648 , G11C2216/14
摘要： Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction.

6. 发明授权

US07106627B2 Nonvolatile semiconductor memory device with redundancy and security information circuitry 有权
标题翻译：具有冗余和安全信息电路的非易失性半导体存储器件
公开(公告)号：US07106627B2
公开(公告)日：2006-09-12
申请号：US11194716
申请日：2005-08-02
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/22 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/3436 , G11C16/3454 , G11C29/70 , G11C29/832 , G11C2211/5621 , G11C2211/5641
摘要： A memory cell array has a first and a second storage area. The first storage area has memory elements selected by an address signal. The second storage area has memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.
摘要翻译：存储单元阵列具有第一和第二存储区域。第一存储区域具有由地址信号选择的存储元件。第二存储区域具有通过控制信号选择的存储元件。控制电路具有熔丝元件。当熔丝元件被熔断时，控制电路在第二存储区域上禁止写入和擦除中的至少一个。

7. 发明申请

US20050265092A1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050265092A1
公开(公告)日：2005-12-01
申请号：US11194716
申请日：2005-08-02
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G06F12/16 , G11C7/00 , G11C11/56 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/34 , G11C29/00 , G11C29/04 , G11C29/06 , G11C29/42
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/3436 , G11C16/3454 , G11C29/70 , G11C29/832 , G11C2211/5621 , G11C2211/5641
摘要： A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.
摘要翻译：存储单元阵列具有第一和第二存储区域。第一存储区具有由地址信号选择的存储元件。第二存储区域具有由控制信号选择的存储元件。控制电路具有熔丝元件。当熔丝元件被熔断时，控制电路在第二存储区域上禁止写入和擦除中的至少一个。

8. 发明授权

US06657891B1 Semiconductor memory device for storing multivalued data 有权
标题翻译：用于存储多值数据的半导体存储器件
公开(公告)号：US06657891B1
公开(公告)日：2003-12-02
申请号：US10358643
申请日：2003-02-04
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C1604
CPC分类号： G11C16/3459 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/12 , G11C2211/5642 , G11C2211/5648
摘要： Before the next data is stored into a first memory cell in which i bits of data have been stored, i or less bits of data are written into cells adjacent to the first memory cell beforehand. The writing of i or less bits of data is done using a threshold voltage lower than the original threshold voltage (or the actual threshold voltage in storing i bits of data). After the adjacent cells have been written into, writing is done to raise the threshold voltage of the first memory cell.
摘要翻译：在下一个数据被存储到已经存储了i个比特数据的第一存储单元中之前，预先将I或更少的数据位写入与第一存储单元相邻的单元。使用低于原始阈值电压（或存储i位数据的实际阈值电压）的阈值电压来完成I或更少数据位的写入。在相邻单元被写入之后，进行写入以提高第一存储单元的阈值电压。

9. 发明授权

US06650578B2 Semiconductor storage device and setting method thereof 有权
标题翻译：半导体存储装置及其设定方法
公开(公告)号：US06650578B2
公开(公告)日：2003-11-18
申请号：US10229147
申请日：2002-08-28
申请人： Masatsugu Kojima , Tomoharu Tanaka , Noboru Shibata
发明人： Masatsugu Kojima , Tomoharu Tanaka , Noboru Shibata
IPC分类号： G11C700
CPC分类号： G11C29/785 , G11C29/808
摘要： A semiconductor storage device includes a main memory cell array and a redundancy memory cell array. The redundancy memory cell array is set to selectively have a replacing area replacing a defective memory cell in the main memory cell array, and a non-replacing area other than the replacing area. Memory cells in the main memory cell array and the redundancy memory cell array are selected and driven by a memory selection circuit. A control section for controlling the memory selection circuit is set to assign main memory addresses to memory cells in the non-replacing area, and use these memory cells as an expansion area of the main memory cell array.
摘要翻译：半导体存储装置包括主存储单元阵列和冗余存储单元阵列。冗余存储单元阵列被设置为选择性地具有替换主存储单元阵列中的有缺陷存储单元的替换区域和替换区域以外的非替换区域。主存储单元阵列和冗余存储单元阵列中的存储单元由存储器选择电路选择和驱动。设置用于控制存储器选择电路的控制部分，以将主存储器地址分配给非替代区域中的存储单元，并将这些存储单元用作主存储单元阵列的扩展区域。

10. 发明授权

US06377485B1 Multi-value semiconductor memory device and reading method thereof 有权
标题翻译：多值半导体存储器件及其读取方法
公开(公告)号：US06377485B1
公开(公告)日：2002-04-23
申请号：US09721385
申请日：2000-11-22
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C1634
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C2211/5621 , G11C2211/5642
摘要： For a verify operation using potential Vbi′, the data of a memory cell is preliminarily read by using potential Vai+1 and the state of the memory cell is stored in a latch circuit. Then, a verify/read operation is conducted by using potential Vbi′. If the state of the cell is higher than Ai+1, the outcome of the verify/read operation is forcibly brought down to a low level. Thus, only two latch circuits are required for storing an n-bit data, including one for storing the data to be written and one for preliminarily reading if the state of the cell is higher than Ai+1 or not and storing the outcome of the preliminary reading.
摘要翻译：对于使用电位Vbi'的验证操作，通过使用电位Vai + 1预先读取存储单元的数据，并将存储单元的状态存储在锁存电路中。然后，通过使用电位Vbi'进行验证/读取操作。如果单元的状态高于Ai + 1，则验证/读取操作的结果被强制降低到低水平。因此，只需要两个锁存电路来存储n位数据，包括一个用于存储要写入的数据的数据，一个用于在小区的状态高于Ai + 1时预先读取，并且存储初步阅读。

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