专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06650578B2 Semiconductor storage device and setting method thereof 有权
标题翻译：半导体存储装置及其设定方法
公开(公告)号：US06650578B2
公开(公告)日：2003-11-18
申请号：US10229147
申请日：2002-08-28
申请人： Masatsugu Kojima , Tomoharu Tanaka , Noboru Shibata
发明人： Masatsugu Kojima , Tomoharu Tanaka , Noboru Shibata
IPC分类号： G11C700
CPC分类号： G11C29/785 , G11C29/808
摘要： A semiconductor storage device includes a main memory cell array and a redundancy memory cell array. The redundancy memory cell array is set to selectively have a replacing area replacing a defective memory cell in the main memory cell array, and a non-replacing area other than the replacing area. Memory cells in the main memory cell array and the redundancy memory cell array are selected and driven by a memory selection circuit. A control section for controlling the memory selection circuit is set to assign main memory addresses to memory cells in the non-replacing area, and use these memory cells as an expansion area of the main memory cell array.
摘要翻译：半导体存储装置包括主存储单元阵列和冗余存储单元阵列。冗余存储单元阵列被设置为选择性地具有替换主存储单元阵列中的有缺陷存储单元的替换区域和替换区域以外的非替换区域。主存储单元阵列和冗余存储单元阵列中的存储单元由存储器选择电路选择和驱动。设置用于控制存储器选择电路的控制部分，以将主存储器地址分配给非替代区域中的存储单元，并将这些存储单元用作主存储单元阵列的扩展区域。

2. 发明申请

US20120163091A1 SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL 有权
标题翻译：存储细胞中的数据的半导体存储器件
公开(公告)号：US20120163091A1
公开(公告)日：2012-06-28
申请号：US13413779
申请日：2012-03-07
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5648
摘要： A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k
摘要翻译：存储单元阵列被配置为具有以矩阵形式布置的多个存储单元，每个存储单元连接到字线和位线，并且能够存储n个值（n是等于或大于其的自然数）比3）。控制电路根据输入数据控制字线和位线的电位，并将数据写入存储单元。控制电路在写入操作中将数据写入存储单元中的k值阈值电压（k <= n），对位线进行一次预充电，然后改变字线的电位i次，以验证是否存储器单元已达到i值（i <= k）阈值电压。

3. 发明申请

US20100214852A1 SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL 有权
标题翻译：存储细胞中的数据的半导体存储器件
公开(公告)号：US20100214852A1
公开(公告)日：2010-08-26
申请号：US12775571
申请日：2010-05-07
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/04 , G11C16/02
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5648
摘要： A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k
摘要翻译：存储单元阵列被配置为具有以矩阵形式布置的多个存储单元，每个存储单元连接到字线和位线，并且能够存储n个值（n是等于或大于其的自然数）比3）。控制电路根据输入数据控制字线和位线的电位，并将数据写入存储单元。控制电路在写入操作中将数据写入存储单元中的k值阈值电压（k <= n），对位线进行一次预充电，然后改变字线的电位i次，以验证是否存储器单元已达到i值（i <= k）阈值电压。

4. 发明授权

US07509566B2 Flash memory 有权
标题翻译：闪存
公开(公告)号：US07509566B2
公开(公告)日：2009-03-24
申请号：US11747225
申请日：2007-05-10
申请人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
发明人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
IPC分类号： H03M13/00 , G11C29/00 , G11C11/34
CPC分类号： G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1072 , G11C7/1006 , G11C16/0483 , G11C16/10 , G11C2029/0411 , G11C2207/104
摘要： A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal.
摘要翻译：闪速存储器包括存储器扇区，命令接口，第一信号缓冲器，控制信号生成电路，数据输入缓冲器，纠错电路，地址缓冲器，地址信号生成电路，多个数据存储电路，和写电路。命令接口从外部设备接收写入数据输入指令，生成写入数据输入指令信号，并从外部设备接收写入指令，生成写入指令信号。误差校正电路由写数据输入指令信号激活，以与写使能信号同步地接收写入数据，并由写指令信号激活，以产生与控制信号同步的纠错校验数据。

5. 发明申请

US20080266965A1 NONVOLATILE SEMICONDUCTOR MEMORY HAVING PLURAL DATA STORAGE PORTIONS FOR A BIT LINE CONNECTED TO MEMORY CELLS 审中-公开
标题翻译：具有连接到存储单元的位线的多个数据存储部分的非易失性半导体存储器
公开(公告)号：US20080266965A1
公开(公告)日：2008-10-30
申请号：US12163676
申请日：2008-06-27
申请人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
发明人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C7/1051 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/12 , G11C16/24 , G11C16/3431 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643 , G11C2211/5649 , G11C2211/565 , G11C2216/14
摘要： Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.
摘要翻译：具有三个以上值的数据以非易失性方式存储在存储单元中。数据电路具有多个存储电路。多个存储电路中的一个是锁存电路。多个存储电路中的另一个是电容器。锁存电路和电容器用于临时存储具有两位或更多位的程序/读数据。如果由于泄漏引起的数据变化导致程序，则使用锁存电路来刷新由电容器保持的数据。结果，即使使用多级数据，数据电路也不会变大。

6. 发明授权

US07342825B2 Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells 有权
公开(公告)号：US07342825B2
公开(公告)日：2008-03-11
申请号：US11690674
申请日：2007-03-23
申请人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
发明人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C7/1051 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/12 , G11C16/24 , G11C16/3431 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643 , G11C2211/5649 , G11C2211/565 , G11C2216/14
摘要： Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.

7. 发明授权

US07315471B2 Semiconductor memory device for storing multivalued data 有权
标题翻译：用于存储多值数据的半导体存储器件
公开(公告)号：US07315471B2
公开(公告)日：2008-01-01
申请号：US11469279
申请日：2006-08-31
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3459 , G11C2211/5621 , G11C2211/5646 , G11C2211/5648 , G11C2216/14
摘要： Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction.
摘要翻译：数据存储电路以一一对应的方式连接到位线。写电路将第一页上的数据写入由字线同时选择的多个第一存储单元。此后，写电路将第二页上的数据写入多个第一存储单元。然后，写入电路将第一和第二页面上的数据写入与位线方向相邻的第一存储单元的第二存储单元。

8. 发明申请

US20070280017A1 Nonvolatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070280017A1
公开(公告)日：2007-12-06
申请号：US11772271
申请日：2007-07-02
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C7/00
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/3436 , G11C16/3454 , G11C29/70 , G11C29/832 , G11C2211/5621 , G11C2211/5641
摘要： A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.
摘要翻译：存储单元阵列具有第一和第二存储区域。第一存储区具有由地址信号选择的存储元件。第二存储区域具有由控制信号选择的存储元件。控制电路具有熔丝元件。当熔丝元件被熔断时，控制电路在第二存储区域上禁止写入和擦除中的至少一个。

9. 发明授权

US07295469B2 Nonvolatile semiconductor memory device with a ROM block settable in a write/erase inhibit mode 有权
标题翻译：具有可设置为写/擦除禁止模式的ROM块的非易失性半导体存储器件
公开(公告)号：US07295469B2
公开(公告)日：2007-11-13
申请号：US11530340
申请日：2006-09-08
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/22
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/3436 , G11C16/3454 , G11C29/70 , G11C29/832 , G11C2211/5621 , G11C2211/5641
摘要： A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.
摘要翻译：存储单元阵列具有第一和第二存储区域。第一存储区具有由地址信号选择的存储元件。第二存储区域具有由控制信号选择的存储元件。控制电路具有熔丝元件。当熔丝元件被熔断时，控制电路在第二存储区域上禁止写入和擦除中的至少一个。

10. 发明申请

US20060146610A1 Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells 有权
公开(公告)号：US20060146610A1
公开(公告)日：2006-07-06
申请号：US11336944
申请日：2006-01-23
申请人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
发明人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C7/1051 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/12 , G11C16/24 , G11C16/3431 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643 , G11C2211/5649 , G11C2211/565 , G11C2216/14
摘要： Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式