专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08679762B2 Method of detecting hepatitis B virus s antigen 有权
标题翻译：检测乙型肝炎病毒抗原的方法
公开(公告)号：US08679762B2
公开(公告)日：2014-03-25
申请号：US11663517
申请日：2005-09-21
申请人： Noboru Maki , Yasuyuki Fukuda , Tatsuji Kimura , Yoko Oda , Chiharu Ohue , Osamu Kusano
发明人： Noboru Maki , Yasuyuki Fukuda , Tatsuji Kimura , Yoko Oda , Chiharu Ohue , Osamu Kusano
IPC分类号： C12Q1/70 , C07H21/04 , A61K39/395
CPC分类号： G01N33/5761 , C07K14/005 , C07K16/082 , C12N2730/10122
摘要： [PROBLEMS] To provide a probe useful in the detection of HBV or HBs antigen by which an escape mutant of hepatitis B virus (HBV) possibly occurring in a specimen can be detected; and a method of using the same.[MEANS FOR SOLVING PROBLEMS] A probe capable of recognizing an epitope located on a peptide comprising the amino acid sequence of SEQ ID NO:1; and a method of detecting hepatitis B virus or hepatitis B virus s antigen by using this probe.
摘要翻译： [问题]提供可用于检测HBV或HBs抗原的探针，通过该探针可以检测可能发生在样品中的乙型肝炎病毒（HBV）的逃逸突变体; 及其使用方法。解决问题的手段能够识别位于包含SEQ ID NO：1的氨基酸序列的肽的表位的探针; 以及通过使用该探针检测乙型肝炎病毒或乙型肝炎病毒抗原的方法。

2. 发明申请

US20080193916A1 Method of Detecting Hepatitis B Virus S Antigen 有权
标题翻译：检测乙型肝炎病毒S抗原的方法
公开(公告)号：US20080193916A1
公开(公告)日：2008-08-14
申请号：US11663517
申请日：2005-09-21
申请人： Noboru Maki , Yasuyuki Fukuda , Tatsuji Kimura , Yoko Oda , Chiharu Ohue , Osamu Kusano
发明人： Noboru Maki , Yasuyuki Fukuda , Tatsuji Kimura , Yoko Oda , Chiharu Ohue , Osamu Kusano
IPC分类号： C12Q1/70 , C07H21/04
CPC分类号： G01N33/5761 , C07K14/005 , C07K16/082 , C12N2730/10122
摘要： [PROBLEMS] To provide a probe useful in the detection of HBV or HBs antigen by which an escape mutant of hepatitis B virus (HBV) possibly occurring in a specimen can be detected; and a method of using the same.[MEANS FOR SOLVING PROBLEMS]A probe capable of recognizing an epitope located on a peptide comprising the amino acid sequence of SEQ ID NO:1; and a method of detecting hepatitis B virus or hepatitis B virus s antigen by using this probe.
摘要翻译： [问题]提供可用于检测HBV或HBs抗原的探针，通过该探针可以检测可能发生在样品中的乙型肝炎病毒（HBV）的逃逸突变体; 及其使用方法。解决问题的手段能够识别位于包含SEQ ID NO：1的氨基酸序列的肽的表位的探针; 以及通过使用该探针检测乙型肝炎病毒或乙型肝炎病毒抗原的方法。

3. 发明授权

US08487526B2 Light emitting apparatus, surface light source apparatus and display apparatus 有权
标题翻译：发光装置，表面光源装置和显示装置
公开(公告)号：US08487526B2
公开(公告)日：2013-07-16
申请号：US13483188
申请日：2012-05-30
申请人： Masao Yamaguchi , Yasuyuki Fukuda
发明人： Masao Yamaguchi , Yasuyuki Fukuda
IPC分类号： H01J1/62 , H01J63/04
CPC分类号： F21V5/04 , B29D11/0048 , B29D11/0074 , B29K2033/12 , B29K2069/00 , B29K2105/20 , F21V13/02 , F21Y2101/00 , F21Y2105/16 , F21Y2115/10 , G02B3/0037 , G02B3/04 , G02B5/0215 , G02B5/0278 , G02B19/0028 , G02B19/0066 , G02F1/133603 , G02F1/133606 , G02F2001/133607 , H01L33/58
摘要： A light emitting apparatus has a light emitting element arranged on a substrate and a light flux controlling member. The light flux controlling member has: a light control/emission surface that controls a traveling direction of light; a concavity that allows a main beam to be incident inside; and a back surface that extends in a radial direction from an opening rim part of the concavity and that allows sub-beams to be incident inside. One of a grid convex part which arranges a plurality of strips of convex parts in a grid pattern and a grid concave part which arranges a plurality of strips of concave parts in a grid pattern is formed in the back surface of the light flux controlling member. The substrate and the back surface of the light flux controlling member are placed opposite to one another without intervention of a reflective sheet therebetween.
摘要翻译：发光装置具有设置在基板上的发光元件和光束控制部件。光束控制部件具有：控制光的行进方向的光控制/发射面; 允许主梁入射到内部的凹面; 以及从凹部的开口边缘部沿径向延伸并且允许副梁入射到内部的背面。在光束控制部件的背面形成有将多个凸条部分排列成格栅图案的网格凸部和栅格图案中的多个凹部排列的网格凹部。光束控制部件的基板和背面彼此相对设置，而不会在其间介入反射片。

4. 发明授权

US08189401B2 Semiconductor memory device and control method of the same 有权
标题翻译：半导体存储器件及其控制方法相同
公开(公告)号：US08189401B2
公开(公告)日：2012-05-29
申请号：US12724882
申请日：2010-03-16
申请人： Yasuyuki Fukuda
发明人： Yasuyuki Fukuda
IPC分类号： G11C7/10 , G11C16/04 , G11C16/06
CPC分类号： G11C16/349 , G11C16/0408
摘要： A semiconductor memory device includes a memory cell array including a plurality of memory cells, a first data latch circuit, a second data latch circuit, an arithmetic circuit, a counter circuit, and a controller. And controller compares the number (N) counted by the counter circuit with a reference number (M), and performs control to output flag information outside if N≧M.
摘要翻译：半导体存储器件包括包括多个存储单元的存储单元阵列，第一数据锁存电路，第二数据锁存电路，运算电路，计数器电路和控制器。并且控制器将计数器电路计数的数量（N）与参考数（M）进行比较，并且如果N≥M，则执行外部输出标志信息的控制。

5. 发明授权

US08328395B2 Light emitting apparatus, surface light source apparatus, display apparatus, and luminous flux control member 有权
标题翻译：发光装置，面光源装置，显示装置和光通量控制部件
公开(公告)号：US08328395B2
公开(公告)日：2012-12-11
申请号：US13165174
申请日：2011-06-21
申请人： Hideaki Kato , Yasuyuki Fukuda
发明人： Hideaki Kato , Yasuyuki Fukuda
IPC分类号： F21V5/04
CPC分类号： G02F1/133603 , G02B19/0014 , G02B19/0061 , G02F2001/133607
摘要： A light emitting apparatus emits light emitted from a light emitting element (200) mounted on a substrate (300) via a luminous flux control member (100). The luminous flux control member (100) has a bottom surface section (101) opposite to the substrate (300), an input surface section (106) for causing the light emitted from a light emitting element (200) to enter inside the input surface section (106), a light control output surface section (102) for refracting the light having entered from the input surface section (106) and outputting the light outside, and two or more leg sections (103) are formed to project outward from the bottom surface section (101) inside a circle with a circumference on which a position where the amount of light reflected by the light control output surface section (102) and yet reaching the bottom surface section (101) peaks is located, and attached to the substrate (300).
摘要翻译：发光装置经由光束控制构件（100）发射从安装在基板（300）上的发光元件（200）发射的光。光通量控制构件（100）具有与基板（300）相对的底面部（101），输入面部（106），其使从发光元件（200）射出的光进入输入面部分（106），用于折射从输入表面部分（106）输入的光并将光输出到外部的光控制输出表面部分（102），以及两个或更多个腿部部分（103）形成为从底面部分（101）在圆周内，圆周上由光控制输出表面部分（102）反射并且到达底表面部分（101）的光的量位于该圆周上，并且附接到基板（300）。

6. 发明授权

US08227969B2 Light emitting apparatus, surface light source apparatus and display apparatus 有权
标题翻译：发光装置，表面光源装置和显示装置
公开(公告)号：US08227969B2
公开(公告)日：2012-07-24
申请号：US12768108
申请日：2010-04-27
申请人： Masao Yamaguchi , Yasuyuki Fukuda
发明人： Masao Yamaguchi , Yasuyuki Fukuda
IPC分类号： H01J5/16 , H01J61/40 , H01K1/26
CPC分类号： F21V5/04 , B29D11/0048 , B29D11/0074 , B29K2033/12 , B29K2069/00 , B29K2105/20 , F21V13/02 , F21Y2101/00 , F21Y2105/16 , F21Y2115/10 , G02B3/0037 , G02B3/04 , G02B5/0215 , G02B5/0278 , G02B19/0028 , G02B19/0066 , G02F1/133603 , G02F1/133606 , G02F2001/133607 , H01L33/58
摘要： A light emitting apparatus can prevent unevenness in illuminance from being produced. This light emitting apparatus 5 has: light emitting elements 3 that emit light; and light flux controlling members 4 that control the traveling directions of light emitted from light emitting elements 3, and a plurality of grid convex parts 13 are formed in back surface 12 (i.e. lens bottom surface) of light flux controlling member 4. Grid convex parts 13 vary the incident angles of light incident on back surface 12 of light flux controlling member 4. Therefore, light incident from back surface 12 is scattered without being concentrated, and is emitted from light flux controlling member 4.
摘要翻译：发光装置可以防止产生不均匀的照度。该发光装置5具有：发光的发光元件3; 控制从发光元件3射出的光的行进方向的光束控制部件4和多个栅格凸部13形成在光束控制部件4的背面12（即透镜底面）上。网格凸部 13改变入射在光束控制构件4的背面12上的光的入射角度。因此，从后表面12入射的光不会集中而散射，并且从光束控制构件4发射。

7. 发明授权

US07881116B2 Nonvolatile semiconductor memory capable of trimming an initial program voltage for each word line 失效
标题翻译：非易失性半导体存储器，能够修整每个字线的初始编程电压
公开(公告)号：US07881116B2
公开(公告)日：2011-02-01
申请号：US12719550
申请日：2010-03-08
申请人： Hiroyuki Nagashima , Yasuyuki Fukuda
发明人： Hiroyuki Nagashima , Yasuyuki Fukuda
IPC分类号： G11C16/12
CPC分类号： G11C16/12 , G11C16/04 , G11C29/02 , G11C29/021 , G11C29/028
摘要： A nonvolatile semiconductor memory of the present invention includes a plurality of bit lines and word lines which are arranged to intersect each other; a memory cell array having a plurality of electrically-programmable memory cells arranged in a region in which the bit lines and the word lines intersect; a trimming circuit configured to obtain a parameter of an initial program voltage for each word line of the plurality of word lines; an initial Vpgm parameter register configured to receive the parameter of the initial program voltage from the trimming circuit and to store the parameter; and a control circuit configured to perform programming of data to the memory cell array based on the parameter of the initial program voltage stored in the initial Vpgm parameter register, the trimming circuit being arranged in a part of the control circuit.
摘要翻译：本发明的非易失性半导体存储器包括被布置为彼此相交的多个位线和字线; 具有布置在所述位线和所述字线相交的区域中的多个电可编程存储单元的存储单元阵列; 修整电路，被配置为获得所述多个字线中的每个字线的初始编程电压的参数; 初始Vpgm参数寄存器，被配置为从修整电路接收初始编程电压的参数并存储该参数; 以及控制电路，被配置为基于存储在初始Vpgm参数寄存器中的初始编程电压的参数来对存储单元阵列执行数据的编程，修整电路被布置在控制电路的一部分中。

8. 发明授权

US07505318B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07505318B2
公开(公告)日：2009-03-17
申请号：US11610193
申请日：2006-12-13
申请人： Yasuyuki Fukuda , Noboru Shibata
发明人： Yasuyuki Fukuda , Noboru Shibata
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/04 , G11C29/82
摘要： A nonvolatile semiconductor memory device of the present invention is characterized in that, when data is written to a flag cell area, every other flag cell in the direction of one bit line BL among a plurality of flag cells 15 connected to the bit line BL is written with data and every other flag cell in the direction of one word line WL among a plurality of flag cells 15 connected to the word line WL is written with data. The arrangement as described above prevents a flag cell 15 from being influenced by the capacitive coupling of a neighboring flag cell 15 adjacent to the flag cell 15 in the direction of the word line WL. Thus, data (flag data) memorized by the flag cell 15 can have improved reliability.
摘要翻译：本发明的非易失性半导体存储器件的特征在于，当数据被写入标志单元区域时，连接到位线BL的多个标志单元15中的一个位线BL的方向上的每隔一个标志单元是在与字线WL连接的多个标志单元15中的一个字线WL的方向上用数据和每隔一个的标志单元写入数据。如上所述的布置防止了标志单元15受到在字线WL的方向上与标志单元15相邻的相邻标记单元15的电容耦合的影响。因此，由标志单元15存储的数据（标志数据）可以提高可靠性。

9. 发明授权

US08300444B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08300444B2
公开(公告)日：2012-10-30
申请号：US12680582
申请日：2008-10-17
申请人： Hiroyuki Nagashima , Koichi Kubo , Yasuyuki Fukuda
发明人： Hiroyuki Nagashima , Koichi Kubo , Yasuyuki Fukuda
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C16/3413 , G11C16/3463 , G11C2013/0073 , G11C2013/0092 , G11C2213/11 , G11C2213/31 , G11C2213/34 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator generates plural types of write pulses for varying the resistance of the variable resistor based on write data. A selection circuit applies write pulses generated by the pulse generator to the memory cell. A sense amplifier executes verify read to the memory cell. A status decision circuit decides the verify result based on the output from the sense amplifier. A control circuit executes additional write to the memory cell based on the verify result from the status decision circuit.
摘要翻译：非易失性半导体存储器件包括以矩阵形式布置的电可擦除可编程非易失性存储单元的存储单元阵列，每个存储单元使用可变电阻器。脉冲发生器产生用于根据写入数据改变可变电阻器的电阻的多种类型的写入脉冲。选择电路将由脉冲发生器产生的写脉冲施加到存储单元。读出放大器对存储单元执行验证读取。状态判定电路根据读出放大器的输出决定验证结果。控制电路基于来自状态判定电路的验证结果对存储器单元执行附加写入。

10. 发明授权

US07688632B2 Nonvolatile semiconductor memory capable of trimming an initial program voltage for each word line 失效
标题翻译：非易失性半导体存储器，能够修整每个字线的初始编程电压
公开(公告)号：US07688632B2
公开(公告)日：2010-03-30
申请号：US11626143
申请日：2007-01-23
申请人： Hiroyuki Nagashima , Yasuyuki Fukuda
发明人： Hiroyuki Nagashima , Yasuyuki Fukuda
IPC分类号： G11C16/12
CPC分类号： G11C16/12 , G11C16/04 , G11C29/02 , G11C29/021 , G11C29/028
摘要： A nonvolatile semiconductor memory of the present invention includes a plurality of bit lines and word lines which are arranged to intersect each other; a memory cell array having a plurality of electrically-programmable memory cells arranged in a region in which the bit lines and the word lines intersect; a trimming circuit configured to obtain a parameter of an initial program voltage for each word line of the plurality of word lines; an initial Vpgm parameter register configured to receive the parameter of the initial program voltage from the trimming circuit and to store the parameter; and a control circuit configured to perform programming of data to the memory cell array based on the parameter of the initial program voltage stored in the initial Vpgm parameter register, the trimming circuit being arranged in a part of the control circuit.
摘要翻译：本发明的非易失性半导体存储器包括被布置为彼此相交的多个位线和字线; 具有布置在所述位线和所述字线相交的区域中的多个电可编程存储单元的存储单元阵列; 修整电路，被配置为获得所述多个字线中的每个字线的初始编程电压的参数; 初始Vpgm参数寄存器，被配置为从修整电路接收初始编程电压的参数并存储该参数; 以及控制电路，被配置为基于存储在初始Vpgm参数寄存器中的初始编程电压的参数来对存储单元阵列执行数据的编程，修整电路被布置在控制电路的一部分中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式