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1. 发明授权

US5587887A Printed circuit board having a configurable voltage supply 失效
标题翻译：具有可配置电压源的印刷电路板
公开(公告)号：US5587887A
公开(公告)日：1996-12-24
申请号：US432227
申请日：1995-05-01
申请人： Noah M. Price , Duane M. P. Takahashi , David C. Buuck
发明人： Noah M. Price , Duane M. P. Takahashi , David C. Buuck
IPC分类号： H05K1/00 , H05K1/02 , H05K1/11
CPC分类号： H05K1/0262 , H05K1/029 , H05K1/0298 , H05K2201/093 , H05K2201/10689
摘要： The present invention is a printed circuit board design having a configurable voltage supply and a method for implementing a configurable voltage supply PCB with a family of circuit designs. The printed circuit board is designed such that voltage supply planes can be configured to match the device requirements for different ICs inserted into the PCB. The PCB comprises electrically isolated conductive layers that are split into a plurality of electrically isolated fixed and undefined voltage planes. The fixed voltage planes are each coupled to a different supply voltage provided by an external power supply. Undefined voltage planes are coupled to fixed voltage planes with insertable conductive jumpers to obtain the desired voltage supply for each voltage plane. The voltage plane configuration of a particular PCB can be changed depending on where jumpers are inserted to accommodate device voltage requirements over a family of devices.
摘要翻译：本发明是具有可配置电压源的印刷电路板设计和用于实现具有一系列电路设计的可配置电压供应PCB的方法。印刷电路板的设计使得电压供应平面可以配置为匹配插入到PCB中的不同IC的器件要求。 PCB包括电隔离的导电层，其被分离成多个电隔离的固定和未定义的电压平面。固定电压平面各自耦合到由外部电源提供的不同电源电压。未定义的电压平面与可插入的导电跳线耦合到固定电压平面，以获得每个电压平面所需的电压电源。特定PCB的电压平面配置可以根据插入跳线的位置而改变，以适应一系列器件的器件电压要求。

2. 发明授权

US5736796A Printed circuit board having split voltage planes 失效
标题翻译：具有分压电压面的印刷电路板
公开(公告)号：US5736796A
公开(公告)日：1998-04-07
申请号：US432233
申请日：1995-05-01
申请人： Noah M. Price , Duane M. P. Takahashi , David C. Buuck
发明人： Noah M. Price , Duane M. P. Takahashi , David C. Buuck
IPC分类号： H05K1/02 , H01B7/30 , H05K1/11
CPC分类号： H05K1/0262 , H05K1/029 , H05K2201/093 , H05K2201/10015 , H05K2201/10196 , H05K2201/10689
摘要： The present invention is a printed circuit board having conductive layers split into electrically isolated voltage supply plane regions each plane region being connectable to an external supply voltage. The voltage supply plane regions are split to reduce the total number of PCB conductive layers. Voltage supply plane regions are configured to match the device voltage requirements and their placement on the PCB. In the case in which a circuit includes a device having two voltage supply requirements, a first set of the device's power supply pins are fixedly coupled to a first voltage supply plane region and a second set of the device's power supply pins are fixedly coupled to a second voltage supply plane region. In this instance, each of the first and second voltage supply plane regions are fixedly connectable to external voltage supplies or to a voltage regulator according to the voltage supply requirements of the device.
摘要翻译：本发明是一种印刷电路板，其具有分成电隔离的电压供应平面区域的导电层，每个平面区域可连接到外部电源电压。分压供电平面区域以减少PCB导电层的总数。电压供应平面区域配置为匹配器件电压要求及其在PCB上的位置。在电路包括具有两个电压供应要求的器件的情况下，器件的电源引脚的第一组固定地耦合到第一电压供应平面区域，并且第二组器件的电源引脚固定地耦合到第二电压供应平面区域。在这种情况下，第一和第二电压供应平面区域中的每一个可以根据设备的电压供应要求固定地连接到外部电压源或电压调节器。

3. 发明授权

US5644760A Printed circuit board processor card for upgrading a processor-based system 失效
标题翻译：用于升级基于处理器的系统的印刷电路板处理器卡
公开(公告)号：US5644760A
公开(公告)日：1997-07-01
申请号：US432906
申请日：1995-05-01
申请人： R. Stephen Polzin , Noah M. Price , Duane M. P. Takahashi
发明人： R. Stephen Polzin , Noah M. Price , Duane M. P. Takahashi
IPC分类号： G06F13/40 , G06F1/04 , G06F13/00
CPC分类号： G06F13/4068
摘要： A printed circuit board (PCB) processor card is described. The processor card includes a processor, its associated processor card system bus, a clock generator, and its associated processor card system clock bus. The processor card is designed to include the elements that are most likely to be upgraded, i.e. the processor and the clock. As such it is particularly useful when employed for system upgrades.
摘要翻译：描述了印刷电路板（PCB）处理器卡。处理器卡包括处理器，其相关联的处理器卡系统总线，时钟发生器及其相关联的处理器卡系统时钟总线。处理器卡被设计为包括最有可能升级的元件，即处理器和时钟。因此，当用于系统升级时，它特别有用。

4. 发明授权

US5909571A Clock distribution for processor and host cards 失效
标题翻译：处理器和主机卡的时钟分配
公开(公告)号：US5909571A
公开(公告)日：1999-06-01
申请号：US699169
申请日：1996-08-19
申请人： R. Stephen Polzin , Noah M. Price , Duane M. P. Takahashi
发明人： R. Stephen Polzin , Noah M. Price , Duane M. P. Takahashi
IPC分类号： G06F1/10 , G06F1/04
CPC分类号： G06F1/10
摘要： The clock configuration of a printed circuit board (PCB) processor card is described. A processor card including a processor, its associated processor card system bus, a clock generator, and its associated processor card system clock bus is optimized by providing various clock configurations and distributions. In one configuration, multiple clock signals are coupled to a system clock bus for distributing to a host card having system devices. In another configuration, multiple clock signals having various clock rates are coupled to the processor device on the processor card.
摘要翻译：描述印刷电路板（PCB）处理器卡的时钟配置。通过提供各种时钟配置和分布来优化包括处理器，其相关联的处理器卡系统总线，时钟发生器及其相关联的处理器卡系统时钟总线的处理器卡。在一种配置中，多个时钟信号耦合到系统时钟总线，用于分配到具有系统设备的主机卡。在另一种配置中，具有各种时钟速率的多个时钟信号被耦合到处理器卡上的处理器设备。

5. 发明授权

US5731999A Method of controlling clamp induced ringing 失效
标题翻译：控制钳位诱发振铃的方法
公开(公告)号：US5731999A
公开(公告)日：1998-03-24
申请号：US383030
申请日：1995-02-03
申请人： Duane M. P. Takahashi
发明人： Duane M. P. Takahashi
IPC分类号： G06F17/50 , G06G7/48
CPC分类号： G06F17/5036
摘要： A method of designing improved CMOS input circuits by understanding and selecting appropriate drive strength for a CMOS output from a previous stage. The method involves modeling the net using HSPICE and including a transit time term to accurately model charge storage, then size drivers as needed to keep the V.sub.ss clamps out of forward conduction. Excessive ringing can cause data errors in the input stage if unterminated, falling edge transitions in such a net can turn on a receiver's V.sub.ss clamp diode (stored charge in the V.sub.ss clamp diode combined with the line's inductance and the receiver's capacitance form an energized resonant circuit which can release energy at a time to cause a data glitch). Currently, XNS simulation miscalculates the ring amplitude by a factor of three. Driver scaling and termination can eliminate the problem by keeping the receiver's V.sub.ss clamp out of forward conduction. Driver sizing can control the problem. Lower current will turn the clamp on for a shorter amount of time, and change the position of the ring. Improved modeling or simulation can allow selection of correct driver sizes and other circuit elements.
摘要翻译：通过了解和选择前一阶段的CMOS输出的适当驱动强度来设计改进的CMOS输入电路的方法。该方法包括使用HSPICE对网络进行建模，并包括通过时间项以准确地模拟电荷存储，然后根据需要对驱动器进行大小，以使Vss钳位不会向前传导。过多的振铃可能导致输入级的数据错误，如果没有终止，这种网络中的下降沿转换可以接通接收机的Vss钳位二极管（Vss钳位二极管中的存储电荷与线路的电感结合，并且接收器的电容形成一个带通的谐振电路其可以一次释放能量以引起数据毛刺）。目前，XNS仿真将环振幅计算在三分之一以内。驱动器缩放和终止可以通过保持接收器的Vss钳位远离正向传导来消除问题。司机大小可以控制问题。较低的电流会使夹具打开一段较短的时间，并改变环的位置。改进的建模或仿真可以允许选择正确的驱动程序大小和其他电路元件。

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