专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08817400B1 Storage device interface for shingled magnetic recording system 有权
标题翻译：用于带状磁记录系统的存储设备接口
公开(公告)号：US08817400B1
公开(公告)日：2014-08-26
申请号：US13287305
申请日：2011-11-02
申请人： Nitin Nangare , Hongying Sheng , Vincent Wong , Gregory Burd
发明人： Nitin Nangare , Hongying Sheng , Vincent Wong , Gregory Burd
IPC分类号： G11B5/09
CPC分类号： G11B5/012 , G11B20/10009
摘要： A data storage device includes a storage medium on which data is stored in overlapping tracks, and a medium controller that directs storage of data on, and reading of data from, the storage medium, including encoding data being stored and decoding data being read. The decoding includes, when reading a first track, cancelling interference from a second track that overlaps the first track. The data storage device also includes a host controller in communication with the medium controller. The host controller includes memory that stores data decoded, and data to be written, by the medium controller. Communication between the medium controller and the host controller includes signals derived from data on said first and second tracks for facilitating the cancelling. A method of operating a data storage device includes, when reading a first track, facilitating the cancelling by communicating signals derived from the data on the first and second tracks.
摘要翻译：数据存储装置包括存储在重叠轨道上的数据的存储介质，以及指示对存储介质进行数据存储和从存储介质读取的数据的介质控制器，包括正在存储的编码数据和正在读取的数据。解码包括当读取第一轨道时，从与第一轨道重叠的第二轨道消除干扰。数据存储装置还包括与介质控制器通信的主机控制器。主机控制器包括由介质控制器存储解码的数据和要写入的数据的存储器。介质控制器和主机控制器之间的通信包括从所述第一和第二轨道上的数据导出的信号，以便于取消。操作数据存储设备的方法包括：当读取第一轨道时，通过传送从第一和第二轨道上的数据得到的信号来促进抵消。

2. 发明申请

US20050034009A1 Architectures, circuits, systems and methods for reducing latency in data communications 有权
标题翻译：用于减少数据通信延迟的架构，电路，系统和方法
公开(公告)号：US20050034009A1
公开(公告)日：2005-02-10
申请号：US10634218
申请日：2003-08-04
申请人： Pantas Sutardja , Lei Wu , Hongying Sheng
发明人： Pantas Sutardja , Lei Wu , Hongying Sheng
IPC分类号： G06F1/04 , G06F13/40
CPC分类号： G06F13/405
摘要： Circuits, architectures, systems and methods for facilitating data communications and/or reducing latency in data communications. The architecture includes a clock recovery loop receiving data from a host device and providing a recovered clock signal, a filter circuit receiving recovered clock signal information and providing a control signal that adjusts the transmitter clock in response to recovered clock signal information and the two clock signals, and a transmitter receiving the control signal and transmitting data to a destination device in accordance with the transmitter clock. The circuitry generally includes a clock alignment block receiving first and second periodic signals and providing a control signal in response thereto, a filter for first periodic signal information, and a logic circuit configured to combine the control signal and the filtered information, thereby providing an adjustment signal for the second periodic signal. The systems generally relate to those that include the present architecture and/or circuit. The method generally includes determining a phase difference between first and second periodic signals, one of the periodic signals being recovered from a data stream; adjusting the other periodic signal in response to the phase difference and filtered information from the recovered periodic signal; and transmitting the data stream in accordance with said adjusted periodic signal. The present invention advantageously eliminates a FIFO memory in the data path, thereby reducing transceiver latency and improving system performance.
摘要翻译：用于促进数据通信和/或减少数据通信中的延迟的电路，架构，系统和方法。该架构包括时钟恢复环路，其接收来自主机设备的数据并提供恢复的时钟信号，滤波器电路接收恢复的时钟信号信息，并提供响应于恢复的时钟信号信息和两个时钟信号调整发射机时钟的控制信号以及接收控制信号并根据发射机时钟向目的地设备发送数据的发射机。电路通常包括时钟对准块，其接收第一和第二周期信号并响应于此提供控制信号，用于第一周期性信号信息的滤波器以及被配置为组合控制信号和滤波信息的逻辑电路，由此提供调整信号用于第二周期信号。系统通常涉及包括本架构和/或电路的系统。该方法通常包括确定第一和第二周期信号之间的相位差，从数据流中恢复一个周期信号; 响应于来自恢复的周期信号的相位差和滤波信息调整另一周期信号; 以及根据所述调整的周期信号发送数据流。本发明有利地消除数据路径中的FIFO存储器，从而减少收发机等待时间并提高系统性能。

3. 发明授权

US08869010B1 Controlling decoder iterations based on measurements of physical variables 有权
标题翻译：基于物理变量的测量来控制解码器迭代
公开(公告)号：US08869010B1
公开(公告)日：2014-10-21
申请号：US13415501
申请日：2012-03-08
申请人： Hongying Sheng , Zining Wu
发明人： Hongying Sheng , Zining Wu
IPC分类号： H03M13/00 , H03M13/03 , H04L1/00 , H03M13/29
CPC分类号： H03M13/2909 , H03M13/1111 , H03M13/1128 , H03M13/2948 , H03M13/2957 , H03M13/3753 , H03M13/3905 , H03M13/41 , H03M13/6331 , H03M13/6343 , H04L1/005 , H04L1/0051 , H04L1/0053
摘要： Apparatus having corresponding methods and storage devices comprise: an iterative decoder configured to generate codewords based on input samples, wherein the iterative decoder is further configured to perform a number of decoding iterations for each codeword, wherein the number of decoding iterations is an integer greater than zero, and wherein the number of decoding iterations does not exceed a limit number; and a sensor configured to generate one or more measurements of a physical variable, wherein the limit number is set in accordance with the one or more measurements generated by the sensor.
摘要翻译：具有相应方法和存储装置的装置包括：配置成基于输入样本生成码字的迭代解码器，其中迭代解码器还被配置为对每个码字执行多个解码迭代，其中解码迭代次数是大于零，并且其中解码迭代的数量不超过限制数; 以及被配置为生成物理变量的一个或多个测量值的传感器，其中根据由传感器产生的一个或多个测量值设定限制数量。

4. 发明授权

US07817366B1 Gain adjustment before zero phase start 有权
标题翻译：零相启动前增益调整
公开(公告)号：US07817366B1
公开(公告)日：2010-10-19
申请号：US11799722
申请日：2007-05-02
申请人： Vasudev V. Pai , Toai Doan , Hongying Sheng
发明人： Vasudev V. Pai , Toai Doan , Hongying Sheng
IPC分类号： G11B5/35
CPC分类号： G11B20/10009 , G11B20/10027 , G11B20/10037 , G11B20/10055 , G11B20/10222 , G11B20/10314 , G11B20/14 , G11B2220/2516 , G11B2220/2562
摘要： A read-channel module includes a variable-gain amplifier (VGA) module, an analog-to-digital converter (ADC) module, an amplitude measuring module, a gain adjusting module, and a zero phase start (ZPS) module. The VGA module has a variable gain, amplifies input signals, and generates amplified signals. The ADC module converts the amplified signals from analog to digital format and generates samples. The amplitude measuring module receives N of the samples and measures amplitudes of the N samples, where N is an integer greater than 1. The gain adjusting module communicates with the amplitude measuring module and selectively adjusts the variable gain of the VGA module based on the amplitudes. The zero phase start (ZPS) module communicates with the amplitude measuring module, receives the samples, and selectively generates phase information from the samples based on the amplitudes.
摘要翻译：读通道模块包括可变增益放大器（VGA）模块，模数转换器（ADC）模块，幅度测量模块，增益调整模块和零相位启动（ZPS）模块。 VGA模块具有可变增益，放大输入信号，并产生放大信号。 ADC模块将放大的信号从模拟转换为数字格式并生成采样。幅度测量模块接收采样的N个并测量N个采样的振幅，其中N是大于1的整数。增益调节模块与振幅测量模块通信，并根据振幅选择性地调节VGA模块的可变增益。零相位启动（ZPS）模块与幅度测量模块通信，接收采样，并根据振幅从采样中选择性地生成相位信息。

5. 发明授权

US07486718B2 Architectures, circuits, systems and methods for reducing latency in data communications 有权
标题翻译：用于减少数据通信延迟的架构，电路，系统和方法
公开(公告)号：US07486718B2
公开(公告)日：2009-02-03
申请号：US10634218
申请日：2003-08-04
申请人： Pantas Sutardja , Lei Wu , Hongying Sheng
发明人： Pantas Sutardja , Lei Wu , Hongying Sheng
IPC分类号： H03K11/00 , H04L25/60 , H04L25/64
CPC分类号： G06F13/405
摘要： Circuits, architectures, systems and methods for facilitating data communications and/or reducing latency in data communications. The architecture includes a clock recovery loop receiving data from a host device and providing a recovered clock signal, a filter circuit receiving recovered clock signal information and providing a control signal that adjusts the transmitter clock in response to recovered clock signal information and the two clock signals, and a transmitter receiving the control signal and transmitting data to a destination device in accordance with the transmitter clock. The circuitry generally includes a clock alignment block receiving first and second periodic signals and providing a control signal in response thereto, a filter for first periodic signal information, and a logic circuit configured to combine the control signal and the filtered information, thereby providing an adjustment signal for the second periodic signal. The systems generally relate to those that include the present architecture and/or circuit. The method generally includes determining a phase difference between first and second periodic signals, one of the periodic signals being recovered from a data stream; adjusting the other periodic signal in response to the phase difference and filtered information from the recovered periodic signal; and transmitting the data stream in accordance with said adjusted periodic signal. The present invention advantageously eliminates a FIFO memory in the data path, thereby reducing transceiver latency and improving system performance.
摘要翻译：用于促进数据通信和/或减少数据通信中的延迟的电路，架构，系统和方法。该架构包括时钟恢复环路，其接收来自主机设备的数据并提供恢复的时钟信号，滤波器电路接收恢复的时钟信号信息，并提供响应于恢复的时钟信号信息和两个时钟信号调整发射机时钟的控制信号以及接收控制信号并根据发射机时钟向目的地设备发送数据的发射机。电路通常包括时钟对准块，其接收第一和第二周期信号并响应于此提供控制信号，用于第一周期性信号信息的滤波器以及被配置为组合控制信号和滤波信息的逻辑电路，由此提供调整信号用于第二周期信号。系统通常涉及包括本架构和/或电路的系统。该方法通常包括确定第一和第二周期信号之间的相位差，从数据流中恢复一个周期信号; 响应于来自恢复的周期信号的相位差和滤波信息调整另一周期信号; 以及根据所述调整的周期信号发送数据流。本发明有利地消除数据路径中的FIFO存储器，从而减少收发机等待时间并提高系统性能。

6. 发明授权

US08618872B1 Filter with controlled cut-off frequency step-down 失效
标题翻译：滤波器具有受控的截止频率降压
公开(公告)号：US08618872B1
公开(公告)日：2013-12-31
申请号：US11367777
申请日：2006-03-03
申请人： Hongying Sheng , Jun Wang
发明人： Hongying Sheng , Jun Wang
IPC分类号： H03B1/00 , H03K5/00 , H04B1/10 , G06G7/19
CPC分类号： H03H7/0153 , H03H7/24
摘要： A filter network having a variable cut-off frequency can be controlled in a way that allows the cut-off frequency to be changed gradually to avoid undesirable transient effects. An impedance network (such as a resistor network) that provides a plurality of impedance values is provided. Logic, and a corresponding method, are provided to change the impedance value gradually, such as on a step-wise basis, to change the cut-off frequency gradually. The size of the impedance step and the duration of the step can be preprogrammed, and may be different for different types of events that trigger the need for a frequency change. It may also be possible for those preprogrammed values to be initial values only, with the values changing under programmed control during the frequency changing process. Other values, such as the initial and target impedance values that determine the initial and target frequency, also may be programmable.
摘要翻译：可以以允许截止频率逐渐改变以避免不期望的瞬态效应的方式来控制具有可变截止频率的滤波器网络。提供了提供多个阻抗值的阻抗网络（例如电阻网络）。提供逻辑和相应的方法以逐渐改变阻抗值，例如逐步地改变截止频率。可以对阻抗步长的尺寸和步长的持续时间进行预编程，并且对于触发需要频率变化的不同类型的事件可以是不同的。这些预编程值也可能仅作为初始值，在频率变化过程中，值在编程控制下变化。其他值，例如确定初始和目标频率的初始和目标阻抗值也可以是可编程的。

7. 发明授权

US08354869B1 Systems and methods for controlling power supply current using clock gating 有权
标题翻译：使用时钟选通控制电源电流的系统和方法
公开(公告)号：US08354869B1
公开(公告)日：2013-01-15
申请号：US13090600
申请日：2011-04-20
申请人： Hongying Sheng , Chen Liu , Wei Cao
发明人： Hongying Sheng , Chen Liu , Wei Cao
IPC分类号： G06F1/04
CPC分类号： G06F1/324 , G06F1/08 , Y02D10/126
摘要： A control system includes a clock gating module and a clock comparison module. The clock gating module is configured to generate a gating signal based on an enable signal, a given period, and a base clock signal having a given frequency. The clock comparison module is configured to generate a gated clock signal based on the base clock signal and the gating signal.
摘要翻译：控制系统包括时钟门控模块和时钟比较模块。时钟选通模块被配置为基于使能信号，给定周期和具有给定频率的基本时钟信号来产生门控信号。时钟比较模块被配置为基于基本时钟信号和门控信号产生门控时钟信号。

8. 发明授权

US07835425B1 Architectures, circuits, systems and methods for reducing latency in data communications 有权
标题翻译：用于减少数据通信延迟的架构，电路，系统和方法
公开(公告)号：US07835425B1
公开(公告)日：2010-11-16
申请号：US12330218
申请日：2008-12-08
申请人： Pantas Sutardja , Lei Wu , Hongying Sheng
发明人： Pantas Sutardja , Lei Wu , Hongying Sheng
IPC分类号： H03K11/00 , H04L25/60 , H04L25/64
CPC分类号： G06F13/405
摘要： Circuits, architectures, systems and methods for facilitating data communications and/or reducing latency in data communications. The architecture includes a clock recovery loop receiving data from a host device and providing a recovered clock signal, a filter circuit receiving recovered clock signal information and providing a control signal that adjusts the transmitter clock in response to recovered clock signal information and the two clock signals, and a transmitter receiving the control signal and transmitting data to a destination device in accordance with the transmitter clock. The circuitry generally includes a clock alignment block receiving first and second periodic signals and providing a control signal in response thereto, a filter for first periodic signal information, and a logic circuit configured to combine the control signal and the filtered information, thereby providing an adjustment signal for the second periodic signal. The systems generally relate to those that include the present architecture and/or circuit. The method generally includes determining a phase difference between first and second periodic signals, one of the periodic signals being recovered from a data stream; adjusting the other periodic signal in response to the phase difference and filtered information from the recovered periodic signal; and transmitting the data stream in accordance with said adjusted periodic signal. The present invention advantageously eliminates a FIFO memory in the data path, thereby reducing transceiver latency and improving system performance.
摘要翻译：用于促进数据通信和/或减少数据通信中的延迟的电路，架构，系统和方法。该架构包括时钟恢复环路，其接收来自主机设备的数据并提供恢复的时钟信号，滤波器电路接收恢复的时钟信号信息，并提供响应于恢复的时钟信号信息和两个时钟信号调整发射机时钟的控制信号以及接收控制信号并根据发射机时钟向目的地设备发送数据的发射机。电路通常包括时钟对准块，其接收第一和第二周期信号并响应于此提供控制信号，用于第一周期性信号信息的滤波器以及被配置为组合控制信号和滤波信息的逻辑电路，由此提供调整信号用于第二周期信号。系统通常涉及包括本架构和/或电路的系统。该方法通常包括确定第一和第二周期信号之间的相位差，从数据流中恢复一个周期信号; 响应于来自恢复的周期信号的相位差和滤波信息调整另一周期信号; 以及根据所述调整的周期信号发送数据流。本发明有利地消除数据路径中的FIFO存储器，从而减少收发机等待时间并提高系统性能。

9. 发明授权

US08489965B1 Long latency protocol for hard disk controller interface 有权
标题翻译：用于硬盘控制器接口的长延迟协议
公开(公告)号：US08489965B1
公开(公告)日：2013-07-16
申请号：US13540313
申请日：2012-07-02
申请人： Hongying Sheng , Job Lam , Kai-Chuan Chang , Jianke Li
发明人： Hongying Sheng , Job Lam , Kai-Chuan Chang , Jianke Li
IPC分类号： G11C29/00
CPC分类号： G06F11/073 , G06F11/0745 , G06F11/0751
摘要： Some of the embodiments of the present disclosure provide a method comprising receiving a stream of codewords from a hard disk controller (HDC), receiving a write gate signal, the write gate signal configured to request a read/write (R/W) channel to write at least a first part of the stream of codewords to a media, and receiving a symbol count signal indicating a number of symbols in the first part of the received stream of codewords. Other embodiments are also described and claimed.
摘要翻译：本公开的一些实施例提供了一种方法，包括从硬盘控制器（HDC）接收码字流，接收写入门信号，写入门信号被配置为请求读/写（R / W）信道将码字流的至少第一部分写入介质，以及接收指示所接收的码字流的第一部分中的符号数量的符号计数信号。还描述和要求保护其他实施例。

10. 发明授权

US08214719B1 Long latency protocol for hard disk controller interface 有权
标题翻译：用于硬盘控制器接口的长延迟协议
公开(公告)号：US08214719B1
公开(公告)日：2012-07-03
申请号：US12181172
申请日：2008-07-28
申请人： Hongying Sheng , Job Lam , Kai-Chuan Chang , Jianke Li
发明人： Hongying Sheng , Job Lam , Kai-Chuan Chang , Jianke Li
IPC分类号： G06F11/00
CPC分类号： G06F11/073 , G06F11/0745 , G06F11/0751
摘要： Some of the embodiments of the present disclosure provide a method comprising receiving a stream of codewords from a hard disk controller (HDC), receiving a write gate signal, the write gate signal configured to request a read/write (R/W) channel to write at least a first part of the stream of codewords to a media, and receiving a symbol count signal indicating a number of symbols in the first part of the received stream of codewords. Other embodiments are also described and claimed.
摘要翻译：本公开的一些实施例提供了一种方法，包括从硬盘控制器（HDC）接收码字流，接收写入门信号，写入门信号被配置为请求读/写（R / W）信道将码字流的至少第一部分写入介质，以及接收指示所接收的码字流的第一部分中的符号数量的符号计数信号。还描述和要求保护其他实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式