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1. 发明专利

JP2007019095A Manufacturing method for semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2007019095A
公开(公告)日：2007-01-25
申请号：JP2005196533
申请日：2005-07-05
申请人： Nissan Motor Co Ltd , Rohm Co Ltd , ローム株式会社 , 日産自動車株式会社
发明人： SHIMOIDA YOSHIO , TANAKA HIDEAKI , HAYASHI TETSUYA , HOSHI MASAKATSU , YAMAGAMI SHIGEHARU , KAWAMOTO NORIAKI , KITO TAKAYUKI , MIURA MINEO , NAKAMURA TAKASHI
IPC分类号： H01L29/12 , H01L29/78
CPC分类号： H01L21/049 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/772 , H01L29/7828
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device having a low on-resistance, a small reverse leakage current, and a high breakdown strength. SOLUTION: The manufacturing method for the semiconductor device manufacturing the semiconductor device having: a hetero semiconductor region 3 being brought into contact with one main surface of an N - SiC drain region 2 on an N + SiC substrate region 1 and having a band gap different from the drain region 2; a gate electrode 7 brought into contact with a part of a junction section between the hetero semiconductor region 3 and the drain region 2 through a gate insulating film 6; a source electrode 8 connected to the hetero semiconductor region 3; and a drain electrode 9 ohmic-connected to the substrate region 1. In the manufacturing method for the semiconductor device, the gate insulating film 6 is nitriding-treated (such as an annealing treatment at a high temperature under an N 2 O-containing atmosphere) after the formation of the gate insulating film 6. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有低导通电阻，小的反向漏电流和高击穿强度的半导体器件的制造方法。解决方案：制造半导体器件的半导体器件的制造方法具有：异质半导体区域3与N - SiC漏极区域2的一个主表面接触， SP> + SiC衬底区域1并且具有与漏极区域2不同的带隙; 栅电极7通过栅极绝缘膜6与异质半导体区域3和漏极区域2之间的接合部分的一部分接触; 连接到异质半导体区域3的源电极8; 以及与基板区域1欧姆连接的漏电极9.在半导体装置的制造方法中，将栅极绝缘膜6进行氮化处理（例如，在N 2℃的高温下进行退火处理， / SB>含O气氛）。形成栅绝缘膜6后，（C）2007，JPO＆INPIT

2. 发明专利

JP2017085848A 電源装置审中-公开
公开(公告)号：JP2017085848A
公开(公告)日：2017-05-18
申请号：JP2015214589
申请日：2015-10-30
申请人：日産自動車株式会社 , Nissan Motor Co Ltd
发明人： TSUGAWA DAI , YAMAGAMI SHIGEHARU
IPC分类号： H02M7/48 , H02M3/28
摘要：【課題】電力を効率よく送ることができる電源装置を提供する。【解決手段】電源装置において、複数の電源から入力された電力を複数の交流電力にそれぞれ変換する複数の電力変換回路と、複数の電力変換回路の交流出力側にそれぞれ電気的に接続され、負荷に電気的に接続された電力伝送線とを備え、複数の電力変換回路により出力される複数の交流電力の周波数は互いに異なっており、電力伝送線を介して負荷に供給される伝送電力は、複数の交流周波数を重畳することで伝送される。【選択図】図1

3. 发明专利

JP2014127487A Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2014127487A
公开(公告)日：2014-07-07
申请号：JP2012280804
申请日：2012-12-25
申请人： Nissan Motor Co Ltd , 日産自動車株式会社
发明人： YAMAGAMI SHIGEHARU , HAYASHI TETSUYA , MARUI TOSHIHARU , GEI AKIRA , EMORI KENTA
IPC分类号： H01L27/04 , H01L21/28 , H01L21/331 , H01L21/337 , H01L21/338 , H01L21/822 , H01L21/8222 , H01L21/8234 , H01L27/06 , H01L27/088 , H01L27/095 , H01L29/06 , H01L29/12 , H01L29/41 , H01L29/732 , H01L29/78 , H01L29/808 , H01L29/812 , H01L29/861 , H01L29/868
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a simple structure and a high breakdown voltage.SOLUTION: The semiconductor device comprises: a drift region 2 of a first conductivity type which is formed on a semiconductor substrate 1; a diffusion region 3 of a second conductivity type which is formed in the drift region 2 so as to be in contact with the principal surface of the drift region 2; a diffusion region 4 of the first conductivity type which is formed in the diffusion region 3 of the second conductivity type so as to be in contact with the principal surface of the drift region 2; a first electrode 5 which is made of a different material from the semiconductor substrate 1 and bonded to the diffusion region 3 of the second conductivity type and the diffusion region 4 of the first conductivity type; a second electrode 6 which is ohmically connected to the diffusion region 3 of the second conductivity type and the diffusion region 4 of the first conductivity type; a protection diode connected between the first electrode 5 and the second electrode 6; and a temperature detection diode which is in antiparallel connection with the protection diode between the first electrode 5 and the second electrode 6.
摘要翻译：要解决的问题：提供具有简单结构和高击穿电压的半导体器件。解决方案：半导体器件包括：形成在半导体衬底1上的第一导电类型的漂移区2; 形成在漂移区域2中以与漂移区域2的主表面接触的第二导电类型的扩散区域3; 第一导电类型的扩散区域4形成在第二导电类型的扩散区域3中以与漂移区域2的主表面接触; 第一电极5，其由与半导体衬底1不同的材料制成并且接合到第二导电类型的扩散区域3和第一导电类型的扩散区域4; 与第二导电类型的扩散区3和第一导电类型的扩散区4欧姆连接的第二电极6; 连接在第一电极5和第二电极6之间的保护二极管; 以及与第一电极5和第二电极6之间的保护二极管反平行连接的温度检测二极管。

4. 发明专利

JP2014053443A Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：JP2014053443A
公开(公告)日：2014-03-20
申请号：JP2012196775
申请日：2012-09-07
申请人： Nissan Motor Co Ltd , 日産自動車株式会社
发明人： YAMAGAMI SHIGEHARU , HAYASHI TETSUYA , MARUI TOSHIHARU , GEI AKIRA
IPC分类号： H01L29/861 , H01L29/868
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can inhibit deterioration in characteristics caused by a damage layer and deterioration in characteristics caused by a position gap of P-type polycrystalline silicon by performing a process of removing or recovering the damage layers formed on lateral faces and bottom faces of grooves.SOLUTION: A semiconductor device manufacturing method comprises: forming grooves 3 at predetermined parts n a principal surface of a first conductivity type drift region 2 formed on a semiconductor substrate 1; depositing a hetero semiconductor 8 on the principal surface of the drift region 2 and on the drift region 2 in the grooves 3; introducing a second conductivity type impurity 9 into the hetero semiconductor 8 on the sidewall part; removing a part of the hetero semiconductor 8 on the principal surface of the drift region 2; and introducing a first conductivity type impurity 10 into the hetero semiconductor 8 on the principal surface of the drift region 2.
摘要翻译：要解决的问题：提供一种半导体器件制造方法，其可以通过执行除去或回收形成的损伤层的工艺来抑制由P型多晶硅的位置间隙引起的由损伤层引起的特性劣化和特性劣化的半导体器件制造方法在半导体衬底1上形成的第一导电型漂移区2的主表面上的预定部分处形成沟槽3; 在漂移区2的主表面和沟槽3中的漂移区2上沉积异质半导体8; 将第二导电型杂质9引入侧壁部分上的异质半导体8; 去除漂移区2的主表面上的异质半导体8的一部分; 并将第一导电型杂质10引入漂移区2的主表面上的异质半导体8中。

5. 发明专利

JP2012129299A Dissimilar material junction-type diode and method for manufacturing the same 有权
标题翻译：二极管材料结型二极管及其制造方法
公开(公告)号：JP2012129299A
公开(公告)日：2012-07-05
申请号：JP2010278044
申请日：2010-12-14
申请人： Nissan Motor Co Ltd , 日産自動車株式会社
发明人： YAMAGAMI SHIGEHARU , HAYASHI TETSUYA
IPC分类号： H01L29/872 , H01L21/329 , H01L29/41 , H01L29/47 , H01L29/861 , H01L29/868
CPC分类号： H01L29/872 , H01L29/0619
摘要： PROBLEM TO BE SOLVED: To improve mechanical strength of an anode electrode 6 against separation while maintaining current-voltage characteristics, in a dissimilar material junction-type diode.SOLUTION: The dissimilar material junction-type diode includes: a semiconductor substrate 1; a first conductivity type drift region 2 formed on the semiconductor substrate 1; the anode electrode 6 joined to a main surface of the drift region 2 and comprising a material of type different from that of a material of the drift region 2; and a cathode electrode 7 connected to the semiconductor substrate 1. A diode is formed by the joining of the drift region 2 and the anode electrode 6. A fitting structure (3, G1) is formed on a main surface of the anode electrode 6 on a side in contact with the drift region 2.
摘要翻译：要解决的问题：为了在不同的材料结型二极管中提高阳极电极6相对于分离的机械强度而保持电流 - 电压特性。解决方案：异种材料结型二极管包括：半导体衬底1; 形成在半导体衬底1上的第一导电型漂移区2; 阳极电极6接合到漂移区域2的主表面并且包括与漂移区域2的材料不同的材料; 以及连接到半导体基板1的阴极电极7.通过接合漂移区域2和阳极电极6形成二极管。在阳极电极6的主表面上形成嵌合结构（3，G1）与漂移区域接触的一方2.版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2010272578A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010272578A
公开(公告)日：2010-12-02
申请号：JP2009120992
申请日：2009-05-19
申请人： Nissan Motor Co Ltd , 日産自動車株式会社
发明人： TANAKA HIDEAKI , HOSHI MASAKATSU , HAYASHI TETSUYA , YAMAGAMI SHIGEHARU , SUZUKI TATSUHIRO
IPC分类号： H01L29/861 , H01L29/47 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To ease concentration of avalanche current in avalanche breakdown and to improve avalanche resistance.
SOLUTION: A hetero-junction diode is constituted of a semiconductor substrate 100 of silicon carbide, in which a semiconductor board 1 of silicon carbide and an epitaxial layer 2 of silicon carbide are laminated, and of a first hetero semiconductor region 3 whose band gap differs from the semiconductor substrate 100, which forms hetero-junction with the semiconductor substrate 100 and is formed of polycrystalline silicon. An anode electrode 6 is bonded to the first hetero semiconductor region 3 in the semiconductor device. When a prescribed reverse bias is applied to the hetero-junction diode, peripheral ends 9 of a hetero-junction region 4 being a junction face between the first hetero-junction region 3 becoming an avalanche breakdown region which avalanche-breaks down and an epitaxial layer 2 are arranged inside peripheral ends 8 of a junction face between the first hetero semiconductor region 3 and the anode electrode 6.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了缓解雪崩击穿中雪崩电流的集中，并提高雪崩阻力。解耦：异质结二极管由碳化硅的半导体基板100构成，其中层叠有碳化硅的半导体基板1和碳化硅的外延层2，以及第一异质半导体区域3，带隙与半导体衬底100不同，半导体衬底100与半导体衬底100形成异质结并且由多晶硅形成。阳极6与半导体器件中的第一异质子半导体区域3接合。当对异质结二极管施加规定的反向偏压时，异质结区域4的外周端9是形成雪崩分解的雪崩击穿区域的第一异质结区域3与外界层 2布置在第一异质半导体区域3和阳极电极6之间的接合面的外周端8内。版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2008306034A Semiconductor device and method for manufacturing semiconductor device 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2008306034A
公开(公告)日：2008-12-18
申请号：JP2007152564
申请日：2007-06-08
申请人： Nissan Motor Co Ltd , 日産自動車株式会社
发明人： TANAKA HIDEAKI , HOSHI MASAKATSU , HAYASHI TETSUYA , YAMAGAMI SHIGEHARU
IPC分类号： H01L21/28 , H01L21/329 , H01L21/336 , H01L29/12 , H01L29/78 , H01L29/861
CPC分类号： H01L21/0485
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having an ohmic electrode and a method for manufacturing the same with broad freedom in process design and high reliability without precipitation of graphite. SOLUTION: The semiconductor device is provided with an N-type silicon carbide epitaxial layer 2 formed on an N-type silicon carbide semiconductor substrate 1 including silicon carbide, and an ohmic region 4 that ohmically contacts the silicon carbide semiconductor substrate 1 and is a substrate of hetero semiconductor layer 30 composing a polycrystal silicon of different bandgap with silicon carbide. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有欧姆电极的半导体器件及其制造方法，具有工艺设计广泛的自由度和高可靠性，而不会沉淀石墨。解决方案：半导体器件设置有形成在包括碳化硅的N型碳化硅半导体衬底1上的N型碳化硅外延层2和与欧姆接触碳化硅半导体衬底1的欧姆区4和是构成与碳化硅不同带隙的多晶硅的异质半导体层30的衬底。版权所有（C）2009，JPO＆INPIT

8. 发明专利

JP2008211042A Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2008211042A
公开(公告)日：2008-09-11
申请号：JP2007047396
申请日：2007-02-27
申请人： Nissan Motor Co Ltd , 日産自動車株式会社
发明人： TANAKA HIDEAKI , HOSHI MASAKATSU , HAYASHI TETSUYA , YAMAGAMI SHIGEHARU
IPC分类号： H01L29/12 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66068 , H01L29/0847 , H01L29/1608 , H01L29/267 , H01L29/7828
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device in which microfabrication is possible, while reducing the on-state resistance. SOLUTION: The method for manufacturing the semiconductor device has a process for forming the surface of a silicon carbide epitaxial layer 2 and a hetero junction, and a first hetero semiconductor layer 3 composed of a polycrystalline silicon, having a band gap different from that of the silicon carbide epitaxial layer 2; a process to form an etching stopper layer 4 comprising silicon oxide which is a material having a different etching rate from that of the polycrystalline silicon, formed in the predetermined position of the surface of the first hetero semiconductor layer 3; a process to form a second hetero semiconductor layer 5 comprising polycrystalline silicon so as to contact the surface of the first hetero semiconductor layer 3 and the etching stopper layer 4; a process for removing the etching stopper layer 4; a process for thermally-oxidizing the first hetero semiconductor layer 3; and a process to remove the thermally oxidized portion of the first hetero semiconductor layer 3 by wet etching. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以在减小导通电阻的同时进行微细加工的半导体器件的制造方法。解决方案：制造半导体器件的方法具有形成碳化硅外延层2和异质结的表面的工艺，以及由多晶硅组成的第一异质半导体层3，其具有不同于碳化硅外延层2的; 形成在第一异质半导体层3的表面的规定位置上形成的与多晶硅的蚀刻速度不同的蚀刻速度的材料的氧化硅的蚀刻停止层4的工序; 形成包含多晶硅以与第一异质半导体层3和蚀刻停止层4的表面接触的第二异质半导体层5的工艺; 去除蚀刻阻挡层4的工序; 用于热氧化第一异质半导体层3的工艺; 以及通过湿法蚀刻去除第一异质半导体层3的热氧化部分的工艺。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2007299862A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007299862A
公开(公告)日：2007-11-15
申请号：JP2006125422
申请日：2006-04-28
申请人： Nissan Motor Co Ltd , 日産自動車株式会社
发明人： SHIMOIDA YOSHIO , HOSHI MASAKATSU , HAYASHI TETSUYA , TANAKA HIDEAKI , YAMAGAMI SHIGEHARU
IPC分类号： H01L27/04 , H01L21/336 , H01L29/12 , H01L29/78
CPC分类号： H01L27/0255 , H01L28/20 , H01L29/1608 , H01L29/161 , H01L29/267 , H01L29/66068 , H01L29/7828 , H01L29/866
摘要： PROBLEM TO BE SOLVED: To provide a hetero junction field effect transistor with large electrostatic resistance, and its manufacturing method.
SOLUTION: For the purpose of preventing electrostatic discharge damage to a field effect transistor 50, an electrostatic discharge protective element 60 and a protective resistor 70 formed on an n
- -type drain region 2 via a field oxide film 8 are constituted as a stacked bidirectional Zener diode of one or a plurality of first-layer n
+ -type polycrystalline silicon regions 14 and a second-layer p
+ -type polycrystalline silicon region 15; and a stacked resistor of one or a plurality of first-layer n
+ -type resistor layers 9 and a second-layer n
+ -type resistor layer 12. One end of the plurality of first-layer n
+ -type polycrystalline silicon regions 14 is connected with an external gate electrode terminal 11, and the other end is connected with a source electrode 7. One end of the plurality of first-layer n
+ -type resistor layers 9 is connected with a gate electrode 6, and the other end is connected with the external gate electrode terminal 11. Each of semiconductor regions on the first and second layers is formed by using a semiconductor film forming a hetero semiconductor region 4 and the gate electrode 6.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供具有大静电电阻的异质结场效应晶体管及其制造方法。解决方案：为了防止对场效应晶体管50的静电放电损坏，通过经由一个或多个第一电极形成在n - SP型漏极区2上的静电放电保护元件60和保护电阻70 场氧化膜8构成为一个或多个第一层n + SP / SP>型多晶硅区域14和第二层p + / SP>型堆叠双向齐纳二极管，型多晶硅区域15; 以及一个或多个第一层n + 型电阻层9和第二层n + 型电阻层12的堆叠电阻。多个第一层n＆lt; SP＆gt; +＆lt; / SP＆gt;型多晶硅区域14与外部栅电极端子11连接，另一端与源电极7连接。多个第一层层间n + 型电阻层9与栅电极6连接，另一端与外部栅电极端子11连接。第一层和第二层上的半导体区域形成通过使用形成异质半导体区域4和栅电极6的半导体膜。（C）2008，JPO＆INPIT

10. 发明专利

JP2007299845A Semiconductor device, and method for manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007299845A
公开(公告)日：2007-11-15
申请号：JP2006125160
申请日：2006-04-28
申请人： Nissan Motor Co Ltd , 日産自動車株式会社
发明人： YAMAGAMI SHIGEHARU , HOSHI MASAKATSU , SHIMOIDA YOSHIO , HAYASHI TETSUYA , TANAKA HIDEAKI
IPC分类号： H01L29/12 , H01L21/28 , H01L21/336 , H01L29/417 , H01L29/78
CPC分类号： H01L29/66068 , H01L21/046 , H01L29/42376 , H01L29/7827
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing semiconductor device and the same semiconductor device in order to manufacture a semiconductor device having improved reliability of a gate insulating film, and having higher current driving capability.
SOLUTION: After forming a polycrystal silicon 4 as a hetero semiconductor region in contact of hetero-junction with a semiconductor base material on the front surface of an epitaxial layer 2 constituting the semiconductor base material, uneven surface on the front surface of the polycrystal silicon 4 is flattened before formation of a gate insulating film 6. Or, as the hetero semiconductor region, an amorphous or a fine crystal hetero semiconductor having a fine crystal grain size is used. Moreover, in the case where the amorphous whose crystal grain sizes are small or fine crystal grain size hetero semiconductor is formed as the hetero semiconductor region, it is allowable that re-crystallization annealing process may be conducted after formation of the film to generate polycrystal silicon from the hetero semiconductor region. A material of the semiconductor base material may be selected from silicon carbide, gallium nitride, and diamond, and a material of the hetero semiconductor region may also be selected from silicon, silicon germanium, germanium, and gallium arsenic.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了制造半导体器件和相同半导体器件的制造方法，以制造具有提高的栅极绝缘膜的可靠性并且具有较高电流驱动能力的半导体器件。解决方案：在构成半导体基材的外延层2的前表面上形成多晶硅4作为异质结与半导体基材接触的异质半导体区域时，多晶硅4在形成栅极绝缘膜6之前变平。或者，作为异质半导体区域，使用具有微细晶粒尺寸的无定形或微细晶体异质半导体。此外，在形成晶粒尺寸小的非晶体或形成微细晶粒尺寸的异质半导体作为异质半导体区域的情况下，可以在形成膜之后进行再结晶退火工艺以产生多晶硅从异质半导体区域。半导体基材的材料可以选自碳化硅，氮化镓和金刚石，并且异质半导体区的材料也可以选自硅，硅锗，锗和镓砷。版权所有（C）2008，JPO＆INPIT

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