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1. 发明申请

US20140119657A1 EFFICIENT IMAGE ANALYSIS APPARATUS AND TECHNIQUE 有权
标题翻译：有效的图像分析设备和技术
公开(公告)号：US20140119657A1
公开(公告)日：2014-05-01
申请号：US13666913
申请日：2012-11-01
申请人： Niraj Gupta , Oren Agam , Benny Eitan , Mostafa Hagog
发明人： Niraj Gupta , Oren Agam , Benny Eitan , Mostafa Hagog
IPC分类号： G06K9/36
CPC分类号： G06K9/4638 , G06T7/11 , G06T7/187 , G06T2200/28
摘要： An apparatus may include a memory, a processor circuit, and a connected component labeling module. The connected component labeling module may be operative of the processor circuit to determine one or more connected components during reading of an image comprising a multiplicity of pixels from the memory, assign a label to a plurality of pixels of the multiplicity of pixels, generate one or more label connections for a respective one or more labels, each label connection linking a higher label to a lowest label for the same connected component, and write to the memory for each label of the one or more labels a lowest label as defined by the label connection for the each label after a label is assigned to each pixel.
摘要翻译：装置可以包括存储器，处理器电路和连接的部件标签模块。连接的组件标注模块可操作于处理器电路，以在从存储器读取包括多个像素的图像的读取期间确定一个或多个连接的组件，将标签分配给多个像素的多个像素，生成一个或多个针对相应的一个或多个标签的更多标签连接，每个标签连接将较高标签链接到相同连接部件的最低标签，并且向该存储器写入一个或多个标签的每个标签，该标签由标签定义将标签分配给每个像素后，每个标签的连接。

2. 发明授权

US08914430B2 Multiply add functional unit capable of executing scale, round, GETEXP, round, GETMANT, reduce, range and class instructions 有权
标题翻译：增加功能单元，能够执行刻度，圆形，GETEXP，圆形，GETMANT，缩小，范围和类指令
公开(公告)号：US08914430B2
公开(公告)日：2014-12-16
申请号：US12890543
申请日：2010-09-24
申请人： Amit Gradstein , Cristina S. Anderson , Zeev Sperber , Simon Rubanovich , Benny Eitan
发明人： Amit Gradstein , Cristina S. Anderson , Zeev Sperber , Simon Rubanovich , Benny Eitan
IPC分类号： G06F7/38 , G06F9/38 , G06F9/30
CPC分类号： G06F7/57 , G06F5/01 , G06F5/012 , G06F7/483 , G06F7/49947 , G06F7/49957 , G06F7/5443 , G06F9/30014 , G06F9/3893
摘要： A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiply-add instruction. The method further includes executing a second instruction with the functional unit. The second instruction is a round instruction.
摘要翻译：描述了涉及用功能单元执行第一指令的方法。第一条指令是乘法加法指令。该方法还包括执行与功能单元的第二指令。第二个指令是一个圆形指令。

3. 发明申请

US20140222883A1 MATH CIRCUIT FOR ESTIMATING A TRANSCENDENTAL FUNCTION 有权
标题翻译：用于估计传统功能的数学电路
公开(公告)号：US20140222883A1
公开(公告)日：2014-08-07
申请号：US13991892
申请日：2011-12-21
申请人： Jose-Alejandro Pineiro , Simon Rubanovich , Benny Eitan , Amit Gradstein , Thomas D. Fletcher
发明人： Jose-Alejandro Pineiro , Simon Rubanovich , Benny Eitan , Amit Gradstein , Thomas D. Fletcher
IPC分类号： G06F7/57 , G06F7/544
CPC分类号： G06F7/57 , G06F1/02 , G06F1/03 , G06F1/0356 , G06F7/544 , G06F7/552 , G06F9/30014 , G06F9/3832 , G06F2101/08 , G06F2101/10 , G06F2101/12 , G06F2207/5521
摘要： A math circuit for computing an estimate of a transcendental function is described. A lookup table storage circuit has stored therein several groups of binary values, where each group of values represents a respective coefficient of a first polynomial that estimates the function to a high precision. A computing circuit uses a portion of a binary value, that is also taken from one of the groups of values, to evaluate a second polynomial that estimates the function to a low precision. Other embodiments are also described and claimed.
摘要翻译：描述了一种用于计算超验函数估计的数学电路。查找表存储电路中存储有几组二进制值，其中每组值表示将功能估计为高精度的第一多项式的相应系数。计算电路使用二进制值的一部分，其也取自值组中的一组，以评估将功能估计为低精度的第二多项式。还描述和要求保护其他实施例。

4. 发明授权

US08694758B2 Mixing instructions with different register sizes 有权
标题翻译：混合使用不同寄存器大小的指令
公开(公告)号：US08694758B2
公开(公告)日：2014-04-08
申请号：US11965667
申请日：2007-12-27
申请人： Doron Orenstien , Zeev Sperber , Robert Valentine , Benny Eitan
发明人： Doron Orenstien , Zeev Sperber , Robert Valentine , Benny Eitan
IPC分类号： G06F9/34
CPC分类号： G06F9/30043 , G06F9/30036 , G06F9/30112 , G06F9/30181 , G06F9/3824 , G06F9/3885
摘要： When legacy instructions, that can only operate on smaller registers, are mixed with new instructions in a processor with larger registers, special handling and architecture are used to prevent the legacy instructions from causing problems with the data in the upper portion of the registers, i.e., the portion that they cannot directly access. In some embodiments, the upper portion of the registers are saved to temporary storage while the legacy instructions are operating, and restored to the upper portion of the registers when the new instructions are operating. A special instruction may also be used to disable this save/restore operation if the new instruction are not going to use the upper part of the registers.
摘要翻译：当只能在较小寄存器上运行的传统指令与具有较大寄存器的处理器中的新指令混合时，使用特殊处理和架构来防止遗留指令在寄存器上部的数据引起问题，即，他们不能直接访问的部分。在一些实施例中，当旧指令正在操作时，寄存器的上部保存到临时存储器中，并且当新指令正在操作时将寄存器的上部部分恢复到寄存器的上部。如果新指令不会使用寄存器的上半部分，也可以使用特殊指令禁用此保存/恢复操作。

5. 发明申请

US20130124834A1 Method and Apparatus for Unpacking Packed Data 有权
公开(公告)号：US20130124834A1
公开(公告)日：2013-05-16
申请号：US13730848
申请日：2012-12-29
申请人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
发明人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

6. 发明申请

US20130117538A1 Method and Apparatus for Unpacking Packed Data 有权
公开(公告)号：US20130117538A1
公开(公告)日：2013-05-09
申请号：US13730839
申请日：2012-12-29
申请人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
发明人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

7. 发明授权

US08396915B2 Processor for performing multiply-add operations on packed data 失效
公开(公告)号：US08396915B2
公开(公告)日：2013-03-12
申请号：US13603370
申请日：2012-09-04
申请人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
发明人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

8. 发明申请

US20120331028A1 PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA 失效
标题翻译：用于在包装数据上执行多重添加操作的处理器
公开(公告)号：US20120331028A1
公开(公告)日：2012-12-27
申请号：US13603370
申请日：2012-09-04
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

9. 发明申请

US20120198210A1 Microprocessor Having Novel Operations 失效
标题翻译：具有新颖操作的微处理器
公开(公告)号：US20120198210A1
公开(公告)日：2012-08-02
申请号：US13444090
申请日：2012-04-11
申请人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
发明人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： A processor. The processor includes a first register for storing a first packed data, a decoder, and a functional unit. The decoder has a control signal input. The control signal input is for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation. The second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder and the register. The functional unit is for performing the pack operation and the unpack operation using the first packed data. The processor also supports a move operation.
摘要翻译：处理器处理器包括用于存储第一打包数据的第一寄存器，解码器和功能单元。解码器具有控制信号输入。控制信号输入用于接收第一控制信号和第二控制信号。第一控制信号用于指示包装操作。第二控制信号用于指示解封装操作。功能单元耦合到解码器和寄存器。功能单元用于使用第一打包数据执行包操作和拆包操作。处理器还支持移动操作。

10. 发明授权

US08185571B2 Processor for performing multiply-add operations on packed data 有权
标题翻译：用于对打包数据执行加法运算的处理器
公开(公告)号：US08185571B2
公开(公告)日：2012-05-22
申请号：US12409275
申请日：2009-03-23
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

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