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1. 发明授权

US07787563B2 Transmitter for wireless applications incorporation spectral emission shaping sigma delta modulator 有权
标题翻译：用于无线应用的发射机并入光谱发射整形Σ-Δ调制器
公开(公告)号：US07787563B2
公开(公告)日：2010-08-31
申请号：US11297524
申请日：2005-12-07
申请人： Nir Tal , Sameh S. Rezeq , Robert B. Staszewski , Oren E. Eliezer , Ofer Friedman
发明人： Nir Tal , Sameh S. Rezeq , Robert B. Staszewski , Oren E. Eliezer , Ofer Friedman
IPC分类号： H04L25/49
CPC分类号： H03M7/3017 , H03M7/3022 , H03M7/3042
摘要： A transmitter employing a sigma delta modulator having a noise transfer function adapted to shift quantization noise outside at least one frequency band of interest. A technique is presented to synthesize the controllers within a single-loop sigma delta modulator such that the noise transfer function can be chosen arbitrarily from a family of functions satisfying certain conditions. Using the novel modulator design technique, polar and Cartesian (i.e. quadrature) transmitter structures are supported. A transmitter employing polar transmit modulation is presented that shapes the spectral emissions of the digitally-controlled power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands. Similarly, a transmitter employing Cartesian transmit modulation is presented that shapes the spectral emissions of a hybrid power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands.
摘要翻译：一种采用具有噪声传递函数的Σ-Δ调制器的发射机，其适于在至少一个感兴趣的频带之外移位量化噪声。提出了一种用于合成单环Σ-Δ调制器中的控制器的技术，使得噪声传递函数可以从满足某些条件的函数族中任意选择。使用新颖的调制器设计技术，支持极坐标和笛卡尔（即正交）发射机结构。呈现采用极性发射调制的发射机，其对数字控制的功率放大器的频谱发射进行整形，使得它们在一个或多个期望的频带中显着且充分衰减。类似地，呈现采用笛卡尔发射调制的发射机，其对混合功率放大器的频谱发射进行整形，使得它们在一个或多个期望的频带中显着且充分衰减。

2. 发明授权

US09020454B2 Linearization and calibration predistortion of a digitally controlled power amplifier 有权
标题翻译：数字控制功率放大器的线性化和校准预失真
公开(公告)号：US09020454B2
公开(公告)日：2015-04-28
申请号：US13481450
申请日：2012-05-25
申请人： Khurram Waheed , Robert B. Staszewski , Sameh S. Rezeq , Oren E. Eliezer
发明人： Khurram Waheed , Robert B. Staszewski , Sameh S. Rezeq , Oren E. Eliezer
IPC分类号： H04B1/04
CPC分类号： H04B1/0475 , H03F1/3241 , H04B2001/0425
摘要： An apparatus and method of linearization of a digitally-controlled pre-power amplifier (DPA) and RF power amplifier (PA) for performing predistortion calibration to compensate for nonlinearlities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital-to-frequency converter (DFC), DPA and PA. The on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, demodulates the RF PA output and uses the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. A sample of the RF output signal is provided to the receiver chain. While the PA (DPA) code is increasing (or decreasing), the amplitude and phase of the recovered I/Q samples are used to determine the instantaneous value of the AM/AM and AM/PM pre-distortion from which an update to the predistortion tables may be computed.
摘要翻译：用于执行预失真校准以补偿DPA和PA电路中的非线性的数字控制的预功率放大器（DPA）和RF功率放大器（PA）的线性化的装置和方法。预失真查询表（LUT）存储在被输入到数字 - 频率转换器（DFC），DPA和PA之前施加到TX数据的测量失真补偿数据。在半双工操作期间TX突发期间通常不工作的片上接收器解调RF PA输出并使用数字I / Q RX输出来执行TX预失真表的校准。将RF输出信号的样本提供给接收器链。当PA（DPA）代码正在增加（或减小）时，恢复的I / Q采样的振幅和相位用于确定AM / AM和AM / PM预失真的瞬时值，可以计算预失真表。

3. 发明申请

US20070190952A1 LINEARIZATION OF A TRANSMIT AMPLIFIER 有权
标题翻译：发射放大器的线性化
公开(公告)号：US20070190952A1
公开(公告)日：2007-08-16
申请号：US11675582
申请日：2007-02-15
申请人： Khurram Waheed , Robert B. Staszewski , Sameh S. Rezeq , Oren E. Eliezer
发明人： Khurram Waheed , Robert B. Staszewski , Sameh S. Rezeq , Oren E. Eliezer
IPC分类号： H04B1/04
CPC分类号： H04B1/0475 , H03F1/3241 , H04B2001/0425
摘要： A novel apparatus and method of linearization of a digitally controlled pre-power amplifier (DPA) and RF power amplifier (PA). The mechanism is operative to perform predistortion calibration to compensate for nonlinearities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital to frequency converter (DFC), DPA and PA. The mechanism of the invention takes advantage of the on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, to demodulate the RF PA output and use the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. Controlled RF coupling is used to provide a sample of the RF output signal that to the receiver chain. The contents of the predistortion LUT are typically updated during the PA power up or down ramp. While the digitally-controlled PA (DPA) code is increasing (or decreasing), the amplitude and phase of the recovered I/Q samples are used to determine the instantaneous value of the AM/AM and AM/PM pre-distortion from which an update to the predistortion tables may be computed.
摘要翻译：一种数字控制的预功率放大器（DPA）和RF功率放大器（PA）的线性化的新型装置和方法。该机制可用于执行预失真校准，以补偿DPA和PA电路中的非线性。预失真查询表（LUT）存储在被输入到数字到频率转换器（DFC），DPA和PA之前施加到TX数据的测量失真补偿数据。本发明的机制利用在半双工操作期间的TX突发期间通常不工作的片上接收机来解调RF PA输出并使用数字I / Q RX输出来执行TX的校准预失真表。受控RF耦合用于向接收机链提供RF输出信号的采样。预失真LUT的内容通常在PA上电或下降斜坡期间更新。当数字控制的PA（DPA）码增加（或减小）时，恢复的I / Q采样的振幅和相位用于确定AM / AM和AM / PM预失真的瞬时值，可以计算对预失真表的更新。

4. 发明申请

US20120263256A1 LINEARIZATION OF A TRANSMIT AMPLIFIER 审中-公开
标题翻译：发射放大器的线性化
公开(公告)号：US20120263256A1
公开(公告)日：2012-10-18
申请号：US13481450
申请日：2012-05-25
申请人： Khurram Waheed , Robert B. Staszewski , Sameh S. Rezeq , Oren E. Eliezer
发明人： Khurram Waheed , Robert B. Staszewski , Sameh S. Rezeq , Oren E. Eliezer
IPC分类号： H04L25/49
CPC分类号： H04B1/0475 , H03F1/3241 , H04B2001/0425
摘要： An apparatus and method of linearization of a digitally-controlled pre-power amplifier (DPA) and RF power amplifier (PA) for performing predistortion calibration to compensate for nonlinearlities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital-to-frequency converter (DFC), DPA and PA. The on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, demodulates the RF PA output and uses the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. A sample of the RF output signal is provided to the receiver chain. While the PA (DPA) code is increasing (or decreasing), the amplitude and phase of the recovered I/Q samples are used to determine the instantaneous value of the AM/AM and AM/PM pre-distortion from which an update to the predistortion tables may be computed.
摘要翻译：用于执行预失真校准以补偿DPA和PA电路中的非线性的数字控制的预功率放大器（DPA）和RF功率放大器（PA）的线性化的装置和方法。预失真查询表（LUT）存储在被输入到数字 - 频率转换器（DFC），DPA和PA之前施加到TX数据的测量失真补偿数据。在半双工操作期间TX突发期间通常不工作的片上接收器解调RF PA输出并使用数字I / Q RX输出来执行TX预失真表的校准。将RF输出信号的样本提供给接收器链。当PA（DPA）代码正在增加（或减小）时，恢复的I / Q采样的振幅和相位用于确定AM / AM和AM / PM预失真的瞬时值，可以计算预失真表。

5. 发明授权

US08195103B2 Linearization of a transmit amplifier 有权
标题翻译：发射放大器的线性化
公开(公告)号：US08195103B2
公开(公告)日：2012-06-05
申请号：US11675582
申请日：2007-02-15
申请人： Khurram Waheed , Robert B. Staszewski , Sameh S. Rezeq , Oren E. Eliezer
发明人： Khurram Waheed , Robert B. Staszewski , Sameh S. Rezeq , Oren E. Eliezer
IPC分类号： H04B1/04
CPC分类号： H04B1/0475 , H03F1/3241 , H04B2001/0425
摘要： A novel apparatus and method of linearization of a digitally controlled pre-power amplifier (DPA) and RF power amplifier (PA). The mechanism is operative to perform predistortion calibration to compensate for nonlinearities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital to frequency converter (DFC), DPA and PA. The mechanism of the invention takes advantage of the on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, to demodulate the RF PA output and use the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. Controlled RF coupling is used to provide a sample of the RF output signal that to the receiver chain. The contents of the predistortion LUT are typically updated during the PA power up or down ramp. While the digitally-controlled PA (DPA) code is increasing (or decreasing), the amplitude and phase of the recovered I/Q samples are used to determine the instantaneous value of the AM/AM and AM/PM pre-distortion from which an update to the predistortion tables may be computed.
摘要翻译：一种数字控制的预功率放大器（DPA）和RF功率放大器（PA）的线性化的新型装置和方法。该机制可用于执行预失真校准，以补偿DPA和PA电路中的非线性。预失真查询表（LUT）存储在被输入到数字到频率转换器（DFC），DPA和PA之前施加到TX数据的测量失真补偿数据。本发明的机制利用在半双工操作期间TX突发期间通常不活动的片上接收机来解调RF PA输出并使用数字I / Q RX输出来执行TX的校准预失真表。受控RF耦合用于向接收机链提供RF输出信号的采样。预失真LUT的内容通常在PA上电或下降斜坡期间更新。当数字控制的PA（DPA）码增加（或减小）时，恢复的I / Q采样的振幅和相位用于确定AM / AM和AM / PM预失真的瞬时值，可以计算对预失真表的更新。

6. 发明授权

US08463189B2 Predistortion calibration and built in self testing of a radio frequency power amplifier using subharmonic mixing 有权
标题翻译：使用次谐波混合的射频功率放大器的预失真校准和内置自检
公开(公告)号：US08463189B2
公开(公告)日：2013-06-11
申请号：US11831948
申请日：2007-07-31
申请人： Imran Bashir , Robert B. Staszewski , Oren E. Eliezer
发明人： Imran Bashir , Robert B. Staszewski , Oren E. Eliezer
IPC分类号： H04W16/14
CPC分类号： H03F3/217 , H03F1/3241 , H03F3/24 , H04B17/13
摘要： A novel and useful apparatus for and method of predistortion calibration and built-in self testing (BIST) of a nonlinear digitally-controlled radio frequency (RF) power amplifier (DPA) using subharmonic mixing. The RF power amplifier output is temporarily coupled into the frequency reference (FREF) input and the phase error samples generated in the phase locked loop (PLL) are then observed and analyzed. The digital predistortion and BIST mechanisms process the phase error samples to calibrate and test the DPA in the transmitter of the Digital RF Processor (DRP). The invention enables the characterization of nonlinearities, the configuration of internal predistortion, as well as the testing of the transmitter's analogRF circuitry, thereby eliminating commonly employed RF performance testing using high-cost test equipment and associated extended test times.
摘要翻译：一种使用次谐波混合的非线性数字控制射频（RF）功率放大器（DPA）的预失真校准和内置自检（BIST）的新颖有用的装置和方法。 RF功率放大器输出暂时耦合到频率参考（FREF）输入，然后观察和分析在锁相环（PLL）中产生的相位误差采样。数字预失真和BIST机制处理相位误差样本，以校准和测试数字RF处理器（DRP）发射器中的DPA。本发明使得能够表征非线性，内部预失真的配置以及发射机的analogRF电路的测试，从而消除了使用高成本测试设备和相关联的扩展测试时间的通常使用的RF性能测试。

7. 发明申请

US20120252382A1 PREDISTORTION CALIBRATION AND BUILT IN SELF TESTING OF A RADIO FREQUENCY POWER AMPLIFIER USING SUBHARMONIC MIXING 有权
标题翻译：使用次谐波混频的无线电频率放大器的自检校准和内置自测
公开(公告)号：US20120252382A1
公开(公告)日：2012-10-04
申请号：US11831948
申请日：2007-07-31
申请人： Imran Bashir , Robert B. Staszewski , Oren E. Eliezer
发明人： Imran Bashir , Robert B. Staszewski , Oren E. Eliezer
IPC分类号： H04B17/00 , H04W88/02 , H04B1/04
CPC分类号： H03F3/217 , H03F1/3241 , H03F3/24 , H04B17/13
摘要： A novel and useful apparatus for and method of predistortion calibration and built-in self testing (BIST) of a nonlinear digitally-controlled radio frequency (RF) power amplifier (DPA) using subharmonic mixing. The RF power amplifier output is temporarily coupled into the frequency reference (FREF) input and the phase error samples generated in the phase locked loop (PLL) are then observed and analyzed. The digital predistortion and BIST mechanisms process the phase error samples to calibrate and test the DPA in the transmitter of the Digital RF Processor (DRP). The invention enables the characterization of nonlinearities, the configuration of internal predistortion, as well as the testing of the transmitter's analog/RF circuitry, thereby eliminating commonly employed RF performance testing using high-cost test equipment and associated extended test times.
摘要翻译：一种使用次谐波混合的非线性数字控制射频（RF）功率放大器（DPA）的预失真校准和内置自检（BIST）的新颖有用的装置和方法。 RF功率放大器输出暂时耦合到频率参考（FREF）输入，然后观察和分析在锁相环（PLL）中产生的相位误差采样。数字预失真和BIST机制处理相位误差样本，以校准和测试数字RF处理器（DRP）发射器中的DPA。本发明使得能够表征非线性，内部预失真的配置以及发射机的模拟/ RF电路的测试，从而消除了使用高成本测试设备和相关联的扩展测试时间的通常使用的RF性能测试。

8. 发明申请

US20120244824A1 MINIMIZATION OF RMS PHASE ERROR IN A PHASE LOCKED LOOP BY DITHERING OF A FREQUENCY REFERENCE 审中-公开
标题翻译：通过频率参考的最小化在相位锁定环路中的RMS相位误差
公开(公告)号：US20120244824A1
公开(公告)日：2012-09-27
申请号：US11832292
申请日：2007-08-01
申请人： Manouchehr Entezari , Robert B. Staszewski , Thomas Almholt , Oren E. Eliezer
发明人： Manouchehr Entezari , Robert B. Staszewski , Thomas Almholt , Oren E. Eliezer
IPC分类号： H04B15/00 , H04B1/04
CPC分类号： H03L7/1806 , H03L2207/50
摘要： A novel and useful apparatus for and method of minimizing the phase distortions experienced at the output of a phase locked loop (PLL) by dithering of its input frequency reference to overcome additive interference that is parasitically suffered on it. The frequency reference signal is dithered in a controlled manner using either indirect or direct coupling. The dither signal may be a single clock or is generated by switching between two or more of the existing clock signals generated, or may be produced by a dedicated pseudo-random noise generator having specific spectral properties. In indirect coupling, the dither signal is coupled through a bond wire sufficiently close in proximity to the frequency reference circuit input. This dominates the jitter inflicted onto the frequency reference signal and upconverts its spectral content to higher frequency, thus eliminating the more damaging low-frequency jitter caused by the interfering RF signal. In direct coupling, the dither signal is coupled to the reference frequency input using a network of components directly connected thereto.
摘要翻译：一种用于通过抖动其输入频率参考来最小化在锁相环（PLL）的输出处经历的相位失真的新颖且有用的装置，以克服寄生在其上的附加干扰。频率参考信号以受控的方式使用间接或直接耦合进行抖动。抖动信号可以是单个时钟，或者是通过在所生成的两个或更多个现有时钟信号之间进行切换来产生，或者可以由具有特定频谱特性的专用伪随机噪声发生器产生。在间接耦合中，抖动信号通过在频率参考电路输入附近足够接近的接合线耦合。这支配着对频率参考信号造成的抖动，并将其频谱内容上变频到更高的频率，从而消除了由干扰RF信号引起的更有害的低频抖动。在直接耦合中，抖动信号使用直接与其连接的部件的网络耦合到参考频率输入。

9. 发明授权

US07460612B2 Method and apparatus for a fully digital quadrature modulator 有权
标题翻译：全数字正交调制器的方法和装置
公开(公告)号：US07460612B2
公开(公告)日：2008-12-02
申请号：US11203504
申请日：2005-08-11
申请人： Oren E. Eliezer , Francis P. Cruise , Robert B. Staszewski , Jaimin Mehta
发明人： Oren E. Eliezer , Francis P. Cruise , Robert B. Staszewski , Jaimin Mehta
IPC分类号： H04L27/00
CPC分类号： H03F3/24 , H03C3/40 , H03C5/00 , H03F2200/324 , H03F2200/331 , H03F2200/336 , H04K1/02 , H04L27/04 , H04L27/2092 , H04L27/365
摘要： A novel apparatus and method for a fully digital quadrature architecture for a complex modulator. The complex modulator can substitute for existing prior art analog quadrature modulator structures and those based on a digital polar architecture (r, θ). The modulator effectively operates as a complex digital-to-analog converter where the digital inputs are given in Cartesian form, namely I and Q representing the complex number I+jQ, while the output is a modulated RF signal having a corresponding amplitude and phase shift. The phase shift being with respect to a reference phase dictated by the local oscillator, which is also input to the converter/modulator. Several embodiments are provided including modulators incorporating dual I and Q transistor arrays, a single shared I/Q transistor array, modulators with single ended and differential outputs and modulators with single and dual polarity clock and I/Q data signals.
摘要翻译：一种用于复调制器的全数字正交架构的新型装置和方法。复调制器可以替代现有的现有技术的模拟正交调制器结构和基于数字极坐标（r，θ）的那些。调制器有效地作为复数数模转换器工作，其中数字输入以笛卡尔形式给出，即I和Q表示复数I + jQ，而输出是具有对应幅度和相移的调制RF信号。相移相对于由本地振荡器指定的参考相位，本地振荡器也被输入到转换器/调制器。提供了包括具有双I和Q晶体管阵列的调制器，单个共享I / Q晶体管阵列，具有单端和差分输出的调制器以及具有单极性和双极性时钟和I / Q数据信号的调制器的几个实施例。

10. 发明授权

US07466207B2 Gain calibration of a digital controlled oscillator 有权
标题翻译：增益数字控制振荡器的校准
公开(公告)号：US07466207B2
公开(公告)日：2008-12-16
申请号：US11619529
申请日：2007-01-03
申请人： Robert B. Staszewski , Gennady Feygin , Oren E. Eliezer , Dirk Leipold
发明人： Robert B. Staszewski , Gennady Feygin , Oren E. Eliezer , Dirk Leipold
IPC分类号： H03C3/06 , H03L7/091 , H03L7/099
CPC分类号： H03L7/0991 , H03L7/085 , H03L2207/50
摘要： A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.
摘要翻译：一种用于实时估计，校准和跟踪全数字锁相环（ADPLL）中的射频（RF）数字控制振荡器（DCO）的增益的新型装置和方法。 ADPLL调制路径中逆DCO增益的精确设置允许直接宽带频率调制，与ADPLL环路带宽无关。增益校准技术基于最速下降迭代算法，其中相位ADPLL误差被采样并与调制数据相关以产生梯度。然后将梯度缩放并添加到DCO增益乘数的当前值。

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