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1. 发明授权

US07702223B2 Circuit for controlling rotation speed of computer fan 失效
标题翻译：控制电脑风扇转速的电路
公开(公告)号：US07702223B2
公开(公告)日：2010-04-20
申请号：US12036273
申请日：2008-02-24
申请人： Cheng Qian , Ning Wang , Yong-Zhao Huang , Hua Zou
发明人： Cheng Qian , Ning Wang , Yong-Zhao Huang , Hua Zou
IPC分类号： H02P7/00
CPC分类号： G06F1/206
摘要： A circuit for controlling rotation speed of a computer fan includes a fan header for connecting to a 4-pin fan or a 3-pin fan, a jumper device, an amplifier, and a controller. The jumper device has a first pin for receiving a controlling signal, and connected to a first power source, a second pin connected to the fan header, and a third pin connected to the first power source. The amplifier has an input terminal connected to the third pin of the jumper device via an integrator. The controller has a first terminal connected to an output terminal of the amplifier, a second terminal connected to a second power source, and a third terminal connected to the fan header and connected to a positive input terminal of the amplifier via a resistor. The first pin of the jumper device is selectively connected to the second or third pin.
摘要翻译：用于控制计算机风扇的转速的电路包括用于连接到4针风扇或3针风扇的风扇接头，跳线器件，放大器和控制器。跳线装置具有用于接收控制信号的第一引脚，并且连接到第一电源，连接到风扇接头的第二引脚和连接到第一电源的第三引脚。放大器具有通过积分器连接到跳线器件的第三引脚的输入端子。控制器具有连接到放大器的输出端的第一端子，连接到第二电源的第二端子和连接到风扇插座的第三端子，并且经由电阻器连接到放大器的正输入端子。跳线器件的第一引脚选择性地连接到第二引脚或第三引脚。

2. 发明申请

US20090175602A1 CIRCUIT FOR CONTROLLING ROTATION SPEED OF COMPUTER FAN 失效
标题翻译：控制电脑风扇转速的电路
公开(公告)号：US20090175602A1
公开(公告)日：2009-07-09
申请号：US12036273
申请日：2008-02-24
申请人： Cheng Qian , Ning Wang , Yong-Zhao Huang , Hua Zou
发明人： Cheng Qian , Ning Wang , Yong-Zhao Huang , Hua Zou
IPC分类号： H02P7/00
CPC分类号： G06F1/206
摘要： A circuit for controlling rotation speed of a computer fan includes a fan header for connecting to a 4-pin fan or a 3-pin fan, a jumper device, an amplifier, and a controller. The jumper device has a first pin for receiving a controlling signal, and connected to a first power source, a second pin connected to the fan header, and a third pin connected to the first power source. The amplifier has an input terminal connected to the third pin of the jumper device via an integrator. The controller has a first terminal connected to an output terminal of the amplifier, a second terminal connected to a second power source, and a third terminal connected to the fan header and connected to a positive input terminal of the amplifier via a resistor. The first pin of the jumper device is selectively connected to the second or third pin.
摘要翻译：用于控制计算机风扇的转速的电路包括用于连接到4针风扇或3针风扇的风扇接头，跳线器件，放大器和控制器。跳线装置具有用于接收控制信号的第一引脚，并且连接到第一电源，连接到风扇接头的第二引脚和连接到第一电源的第三引脚。放大器具有通过积分器连接到跳线器件的第三引脚的输入端子。控制器具有连接到放大器的输出端的第一端子，连接到第二电源的第二端子和连接到风扇插座的第三端子，并且经由电阻器连接到放大器的正输入端子。跳线器件的第一引脚选择性地连接到第二引脚或第三引脚。

3. 发明申请

US20090161472A1 MEMORY VOLTAGE CONTROL CIRCUIT 有权
标题翻译：内存电压控制电路
公开(公告)号：US20090161472A1
公开(公告)日：2009-06-25
申请号：US12057377
申请日：2008-03-28
申请人： Ning Wang , Cheng Qian , Yong-Zhao Huang
发明人： Ning Wang , Cheng Qian , Yong-Zhao Huang
IPC分类号： G11C5/14 , G05F1/10
CPC分类号： G11C5/147 , G11C11/4072 , G11C11/4074
摘要： A memory voltage control circuit includes two slots, a control circuit, a voltage conversion circuit, and a switch circuit. The two slots are able to efficiently process different memory types. The control circuit receives memory identification signals from the two slots. The control circuit administers the output voltage of the voltage conversion circuit according to the memory identification signals. The memory identification signals determine whether the switch circuit is to be turned on or off. This will control whether the output voltage of the voltage conversion circuit will go to the first or the second slot.
摘要翻译：存储器电压控制电路包括两个时隙，一个控制电路，一个电压转换电路和一个开关电路。这两个插槽能够有效地处理不同的内存类型。控制电路从两个时隙接收存储器识别信号。控制电路根据存储器识别信号来管理电压转换电路的输出电压。存储器识别信号确定开关电路是打开还是关闭。这将控制电压转换电路的输出电压是否将进入第一或第二时隙。

4. 发明授权

US07796459B2 Memory voltage control circuit 有权
标题翻译：内存电压控制电路
公开(公告)号：US07796459B2
公开(公告)日：2010-09-14
申请号：US12057377
申请日：2008-03-28
申请人： Ning Wang , Cheng Qian , Yong-Zhao Huang
发明人： Ning Wang , Cheng Qian , Yong-Zhao Huang
IPC分类号： G11C5/14 , G06F1/00
CPC分类号： G11C5/147 , G11C11/4072 , G11C11/4074
摘要： A memory voltage control circuit includes two slots, a control circuit, a voltage conversion circuit, and a switch circuit. The two slots are able to efficiently process different memory types. The control circuit receives memory identification signals from the two slots. The control circuit administers the output voltage of the voltage conversion circuit according to the memory identification signals. The memory identification signals determine whether the switch circuit is to be turned on or off. This will control whether the output voltage of the voltage conversion circuit will go to the first or the second slot.
摘要翻译：存储器电压控制电路包括两个时隙，一个控制电路，一个电压转换电路和一个开关电路。这两个插槽能够有效地处理不同的内存类型。控制电路从两个时隙接收存储器识别信号。控制电路根据存储器识别信号来管理电压转换电路的输出电压。存储器识别信号确定开关电路是打开还是关闭。这将控制电压转换电路的输出电压是否将进入第一或第二时隙。

5. 发明授权

US07928776B2 Voltage detection device 失效
标题翻译：电压检测装置
公开(公告)号：US07928776B2
公开(公告)日：2011-04-19
申请号：US12195447
申请日：2008-08-21
申请人： Ning Wang , Cheng Qian , Yong-Xing You
发明人： Ning Wang , Cheng Qian , Yong-Xing You
IPC分类号： H03K17/22
CPC分类号： G06F1/26
摘要： An voltage detection device includes a comparator circuit comprising a first input terminal connected to a system power supply, a second input terminal connected to a standby power supply, an output terminal capable of outputting a control voltage according to comparison result; an indicator circuit; and a switch circuit connected between the standby power supply and the indicator circuit, comprising a control terminal to receive the control voltage from the comparator circuit thereby to control the standby power supply supplied to the indicator circuit or not; a power state terminal of the computer connected to a node between the standby power supply and the indicator circuit, wherein the power state terminal is at a low level when the computer is turned off. The voltage detection device can ensure that all the power supplies provide power to the computer components normally.
摘要翻译：电压检测装置包括：比较电路，包括连接到系统电源的第一输入端子，连接到备用电源的第二输入端子，能够根据比较结果输出控制电压的输出端子; 指示电路; 以及连接在备用电源和指示器电路之间的开关电路，包括控制端子，用于从比较器电路接收控制电压，从而控制提供给指示器电路的备用电源; 连接到备用电源和指示器电路之间的节点的计算机的电源状态终端，其中当计算机关闭时，电源状态终端处于低电平。电压检测装置可以确保所有电源正常地为计算机组件供电。

6. 发明授权

US07751158B2 Voltage regulator module control circuit 失效
标题翻译：电压调节器模块控制电路
公开(公告)号：US07751158B2
公开(公告)日：2010-07-06
申请号：US11960753
申请日：2007-12-20
申请人： Cheng Qian , Jin-Liang Xiong , Ning Wang
发明人： Cheng Qian , Jin-Liang Xiong , Ning Wang
IPC分类号： H02H3/22
CPC分类号： H02M3/1584 , H02M1/32
摘要： An exemplary voltage regulator module (VRM) control circuit includes a VRM providing a plurality of phases, each of the phases connected to a control terminal of a corresponding electric switch; a comparator comprising a non-inverting terminal connected to a first power source and grounded via the electric switches respectively, an inverting terminal connected to a reference voltage, and an output terminal; and a control switch connected between an enable terminal of the VRM and ground, the control switch comprising a control terminal connected to the output terminal of the comparator, wherein, if one of the phases of the VRM is lost, the corresponding electric switch is turned off, and a voltage of the non-inverting terminal of the comparator is higher than the reference voltage, the comparator outputs a control signal to the control switch for turning on the control switch, thus turning off the VRM.
摘要翻译：示例性的电压调节器模块（VRM）控制电路包括提供多个相位的VRM，每个相位连接到相应的电开关的控制端; 比较器，其包括连接到第一电源并且经由电开关分别接地的同相端子，连接到参考电压的反相端子和输出端子; 以及控制开关，其连接在所述VRM的使能端子和地之间，所述控制开关包括连接到所述比较器的输出端子的控制端子，其中，如果所述VRM的所述相位之一丢失，则相应的电开关被转动关断，并且比较器的同相端子的电压高于参考电压，比较器向控制开关输出控制信号以接通控制开关，从而关闭VRM。

7. 发明授权

US07850957B2 Adenovirus/alphavirus hybrid vector for the effective administration and expression of therapeutic genes in tumour cells 失效
标题翻译：用于在肿瘤细胞中有效施用和表达治疗基因的腺病毒/甲病毒属杂交载体
公开(公告)号：US07850957B2
公开(公告)日：2010-12-14
申请号：US11569303
申请日：2005-05-18
申请人： Cheng Qian , Min Guan , Cristian Smerdou Picazo , Jesús Prieto Valtueña
发明人： Cheng Qian , Min Guan , Cristian Smerdou Picazo , Jesús Prieto Valtueña
IPC分类号： A01N63/00 , A61K39/12 , C12N15/00
CPC分类号： C12N15/86 , A61K38/208 , A61K48/00 , C12N7/00 , C12N2710/10343 , C12N2770/36143
摘要： The present invention relates to a genic expression adenoviral hybrid vector characterized in that it contains at least the following elements, oriented in the direction 5′ to 3′: i. a first chain of adenoviral origin comprising a first inverted terminal repeat (ITR) sequence and a signal sequence for packaging of the adenovirus; ii. a first non-encoding stuffer sequence; iii. a sequence corresponding to a tissue specific promoter; iv. a chain of cDNA derived from an alphavirus, the sequence of which is partly complementary to an alphaviral RNA sequence, comprising at least a sequence encoding for at least one exogenous gene of interest; v. a polyadenylation sequence; and vi. a second adenoviral inverted terminal repeat (ITR) sequence, it preferably relates to an adenoviral hybrid vector comprising as exogenous gene of interest the therapeutic gene of mammalian interleukin IL-12 and even more preferably human interleukin hIL-12; and to the use of the hybrid vector in a process for transferring genetic material to a cell, particularly a tumor cell that preferably expresses alpha-fetoprotein (AFP), and to its use for inducing an immune response against foreign antigens.
摘要翻译：本发明涉及一种基因表达腺病毒杂合载体，其特征在于其至少包含以5'至3'方向取向的以下元件：i。包括第一反向末端重复序列（ITR）序列和用于包装腺病毒的信号序列的第一个腺病毒源， ii。第一个非编码填充序列; iii。对应于组织特异性启动子的序列; iv。源自甲病毒病毒的cDNA链，其序列与甲病毒RNA序列部分互补，包含至少一个编码至少一种感兴趣的外源基因的序列; v。多腺苷酸化序列; 和vi。第二种腺病毒反向末端重复（ITR）序列，优选涉及包含作为感兴趣的外源基因的哺乳动物白介素IL-12的治疗基因，甚至更优选人白细胞介素hIL-12的腺病毒杂交载体; 以及将遗传物质转移到细胞，特别是优选表达甲胎蛋白（AFP）的肿瘤细胞的方法中以及其用于诱导针对外来抗原的免疫应答的用途的用途。

8. 发明授权

US07600177B2 Delta syndrome based iterative Reed-Solomon product code decoder 有权
标题翻译： Delta迭代Reed-Solomon产品代码解码器
公开(公告)号：US07600177B2
公开(公告)日：2009-10-06
申请号：US11053292
申请日：2005-02-08
申请人： Cheng Qian , Rajesh Juluri
发明人： Cheng Qian , Rajesh Juluri
IPC分类号： H03M13/00
CPC分类号： H03M13/157 , G11B20/1833 , H03M13/1515
摘要： A method for generating syndromes for a data block is disclosed. The method generally includes the steps of (A) calculating a plurality of row syndromes and a plurality of column syndromes for the data block arranged as a Reed-Solomon product code, (B) storing only the row syndromes and the column syndromes in a local memory, (C) in an alternating sequence (i)(a) decoding the column syndromes to generate column correction results and (b) updating the row syndromes in response to the column correction results and (ii)(a) decoding the row syndromes to generate row correction results and (b) updating the column syndromes in response to the row correction results.
摘要翻译：公开了一种用于产生数据块的校正子的方法。该方法通常包括以下步骤：（A）计算多个行综合征和用于数据块的多个列综合征，其被布置为里德 - 所罗门产品代码，（B）仅在本地存储行综合征和列综合征存储器，（C）以交替序列（i）（a）解码列综合征以产生列校正结果;（b）响应于列校正结果更新行综合征，以及（ii）（a）解码行综合征以产生行校正结果和（b）响应于行校正结果更新列综合征。

9. 发明申请

US20070247463A1 Displaying cellular analysis result data using a template 有权
标题翻译：使用模板显示细胞分析结果数据
公开(公告)号：US20070247463A1
公开(公告)日：2007-10-25
申请号：US11408455
申请日：2006-04-21
申请人： Cheng Qian , Ziling Huo , Patricio Vidal
发明人： Cheng Qian , Ziling Huo , Patricio Vidal
IPC分类号： G06T11/20
CPC分类号： G06T7/0012 , G06T11/206 , G06T2207/10056 , G06T2207/30024
摘要： In accordance with the principles of the invention, methods, systems, and computer-readable mediums are provided for displaying cellular analysis result data including accessing cellular analysis result data, accessing data of at least one template, and displaying the cellular analysis result data and the data of at least one template by overlaying the cellular analysis result data and the data of the at least one template, wherein the cellular analysis result data is displayed using different display attributes from the displayed data of the at least one template.
摘要翻译：根据本发明的原理，提供了方法，系统和计算机可读介质，用于显示细胞分析结果数据，包括访问细胞分析结果数据，访问至少一个模板的数据，以及显示细胞分析结果数据和通过覆盖所述细胞分析结果数据和所述至少一个模板的数据来至少一个模板的数据，其中使用与所述至少一个模板的所显示的数据不同的显示属性来显示所述细胞分析结果数据。

10. 发明申请

US20070136641A1 Unified memory architecture for recording applications 失效
标题翻译：用于记录应用程序的统一存储器架构
公开(公告)号：US20070136641A1
公开(公告)日：2007-06-14
申请号：US11299506
申请日：2005-12-12
申请人： Rajesh Juluri , Cheng Qian
发明人： Rajesh Juluri , Cheng Qian
IPC分类号： G11C29/00
CPC分类号： G11B20/1833 , G11B2020/10787 , H03M13/1515
摘要： An apparatus comprising a first circuit configured to (i) extract video data as data blocks from an input signal and (ii) perform error correction on said data blocks with a delta syndrome based iterative Reed-Solomon decoding, a second circuit configured (i) to decode said video data into a video format in a first state, (ii) encode said-video data to write said video data to a disc in a second state and (iii) share an external memory with said first circuit, and a disc configured to store encoded video data.
摘要翻译：一种装置，包括：第一电路，其被配置为：（i）从输入信号中提取视频数据作为数据块，以及（ii）使用基于Δ校正子的迭代Reed-Solomon解码对所述数据块执行纠错;第二电路，将所述视频数据解码成处于第一状态的视频格式，（ii）对所述视频数据进行编码，以将所述视频数据写入到第二状态的盘，以及（iii）与所述第一电路共享外部存储器，以及盘被配置为存储编码的视频数据。

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