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1. 发明申请

US20160093013A1 Reconfigurable Graphics Processor for Performance Improvement 审中-公开
公开(公告)号：US20160093013A1
公开(公告)日：2016-03-31
申请号：US14959455
申请日：2015-12-04
申请人： Nikos Kaburlasos , Eric C. Samson
发明人： Nikos Kaburlasos , Eric C. Samson
IPC分类号： G06T1/20 , G09G5/36 , G06F1/32
CPC分类号： G09G5/36 , G06F1/26 , G06F1/3203 , G06F1/3265 , G06F1/329 , G09G5/363 , G09G2330/021 , G09G2360/06 , G09G2360/08 , Y02D10/153 , Y02D10/24 , Y02D50/20
摘要： Power gating a portion of a graphics processor may be used to improve performance or to achieve a power budget. A processor granularity, such as a slice or subslice, may be gated.

2. 发明申请

US20150035853A1 Partial Tile Rendering 有权
公开(公告)号：US20150035853A1
公开(公告)日：2015-02-05
申请号：US13955228
申请日：2013-07-31
申请人： Nikos Kaburlasos , Eric C. Samson , Robert B. Taylor
发明人： Nikos Kaburlasos , Eric C. Samson , Robert B. Taylor
IPC分类号： G06T1/00
CPC分类号： G06T1/20 , G06T1/00 , G06T1/60 , G09G5/001 , G09G5/363 , G09G5/395 , G09G2330/021 , G09G2360/08 , G09G2360/122 , G09G2360/18
摘要： In accordance with some embodiments, partial rendering of non-changing or slowly changing frame tiles allows the graphics processing unit to spend less time processing non-changing or slowly changing portions of each frame, saving power and creating more room for performance in some embodiments.

3. 发明授权

US10242418B2 Reconfigurable graphics processor for performance improvement 有权
公开(公告)号：US10242418B2
公开(公告)日：2019-03-26
申请号：US13993696
申请日：2011-11-21
申请人： Nikos Kaburlasos , Eric C. Samson
发明人： Nikos Kaburlasos , Eric C. Samson
IPC分类号： G06T1/20 , G09G5/36 , G06F1/32 , G06F1/26 , G06F1/3203 , G06F1/324 , G06F1/3234 , G06F1/3287
摘要： Power gating a portion of a graphics processor may be used to improve performance or to achieve a power budget. A processor granularity, such as a slice or subslice, may be gated.

4. 发明申请

US20120331321A1 Processor Core with Higher Performance Burst Operation with Lower Power Dissipation Sustained Workload Mode 有权
标题翻译：处理器核心，具有更高性能突发操作，功耗更低，持续工作负载模式
公开(公告)号：US20120331321A1
公开(公告)日：2012-12-27
申请号：US13169182
申请日：2011-06-27
申请人： Nikos Kaburlasos , Eric C. Samson , David Puffer , Lakshminarayan Jagannathan
发明人： Nikos Kaburlasos , Eric C. Samson , David Puffer , Lakshminarayan Jagannathan
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3228 , G06F1/3287 , G06F1/3296 , G09G5/363 , G09G2330/021 , G09G2360/08 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： A processor may operate at a first frequency level for a first time interval. The processor automatically may transition to a sleep state from the first frequency level after the first time interval. Then the processor automatically transitions from the sleep state to the first frequency level after a second time interval. As a result the processor may operate at a reduced power consumption and higher performance.
摘要翻译：处理器可以在第一时间间隔的第一频率级别操作。处理器自动地可以在第一时间间隔之后从第一频率电平转换到睡眠状态。然后处理器在第二时间间隔后自动从休眠状态转换到第一频率级。因此，处理器可以以降低的功率消耗和更高的性能来操作。

5. 发明授权

US08924756B2 Processor core with higher performance burst operation with lower power dissipation sustained workload mode 有权
标题翻译：处理器内核具有更高的性能突发操作，功耗更低，持续工作负载模式
公开(公告)号：US08924756B2
公开(公告)日：2014-12-30
申请号：US13169182
申请日：2011-06-27
申请人： Nikos Kaburlasos , Eric C. Samson , David Puffer , Lakshminarayan Jagannathan
发明人： Nikos Kaburlasos , Eric C. Samson , David Puffer , Lakshminarayan Jagannathan
IPC分类号： G06F1/32 , G06F1/26 , G06F1/00 , G06T1/00 , G09G5/36
CPC分类号： G06F1/324 , G06F1/3228 , G06F1/3287 , G06F1/3296 , G09G5/363 , G09G2330/021 , G09G2360/08 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： A processor may operate at a first frequency level for a first time interval. The processor automatically may transition to a sleep state from the first frequency level after the first time interval. Then the processor automatically transitions from the sleep state to the first frequency level after a second time interval. As a result the processor may operate at a reduced power consumption and higher performance.
摘要翻译：处理器可以在第一时间间隔的第一频率级别操作。处理器自动地可以在第一时间间隔之后从第一频率电平转换到睡眠状态。然后处理器在第二时间间隔后自动从休眠状态转换到第一频率级。因此，处理器可以以降低的功率消耗和更高的性能来操作。

6. 发明授权

US08806243B2 Method of and apparatus for energy savings associated with a graphics core 有权
标题翻译：与图形核心相关的节能方法和装置
公开(公告)号：US08806243B2
公开(公告)日：2014-08-12
申请号：US13338354
申请日：2011-12-28
申请人： Nikos Kaburlasos , Eric C. Samson
发明人： Nikos Kaburlasos , Eric C. Samson
IPC分类号： G06F1/32 , G06F9/50
CPC分类号： G06F1/3203 , G06F9/5044 , G06T1/20
摘要： A method includes executing a workload on a graphics (GFX) core in a first mode the GFX core comprising a plurality of Subslices wherein each of the plurality of Subslices dissipates power. The method further includes calculating a number of clock cycles, Tfirst mode, required for the GFX core to perform the workload in the first mode during a first decision window comprising a plurality of clock cycles and calculating a number of clock cycles, Tsecond mode, required for the GFX core to perform the workload in a second mode during the first decision window wherein the second mode comprises executing the workload with fewer of the plurality of Subslices receiving power than when executing the workload in the first mode. It is then determined, based in part upon Tfirst mode and Tsecond mode, if an energy savings is possible by transitioning the GFX core to the second mode.
摘要翻译：一种方法包括在第一模式中执行在图形（GFX）核心上的工作量，所述GFX核心包括多个子片段，其中所述多个子片段中的每一个耗散功率。该方法还包括计算在包括多个时钟周期的第一判定窗口期间GFX核在第一模式中执行工作负载所需的时钟周期数Tfirst模式，并计算需要的时钟周期数Tsecond模式所述GFX核心在所述第一决定窗口期间以第二模式执行所述工作负载，其中所述第二模式包括以比在所述第一模式下执行所述工作负载的情况下更少的所述多个子代理接收功率来执行所述工作负载。然后，部分地基于Tfirst模式和Tsecond模式确定如果通过将GFX核心转换到第二模式可以节省能量。

7. 发明申请

US20140125679A1 Dynamically Rebalancing Graphics Processor Resources 有权
标题翻译：动态重新平衡图形处理器资源
公开(公告)号：US20140125679A1
公开(公告)日：2014-05-08
申请号：US13669576
申请日：2012-11-06
申请人： Nikos Kaburlasos , Eric C. Samson , Altug Koker
发明人： Nikos Kaburlasos , Eric C. Samson , Altug Koker
IPC分类号： G06T1/00
CPC分类号： G06T1/20
摘要： According to some embodiments, performance bottlenecks that arise in particular resources within a graphic processor unit may be alleviated by dynamically rebalancing workloads among the resources, with the goal of removing the current performance bottleneck, while at the same time maintaining power dissipation within a currently allocated power budget. In some embodiments this may be achieved by defining a separate clock domain for each of the plurality of graphics processor resources whose performance may then be rebalanced.
摘要翻译：根据一些实施例，可以通过动态地重新平衡资源之间的工作负载来缓解在图形处理器单元内的特定资源中出现的性能瓶颈，目的是消除当前的性能瓶颈，同时保持当前分配的电力预算在一些实施例中，这可以通过为多个图形处理器资源中的每个图形处理器资源定义单独的时钟域来实现，其中性能可以被重新平衡。

8. 发明申请

US20130286026A1 Reconfigurable Graphics Processor for Performance Improvement 审中-公开
标题翻译：可重构图形处理器，用于性能改进
公开(公告)号：US20130286026A1
公开(公告)日：2013-10-31
申请号：US13993696
申请日：2011-11-21
申请人： Nikos Kaburlasos , Eric C. Samson
发明人： Nikos Kaburlasos , Eric C. Samson
IPC分类号： G06T1/20
CPC分类号： G06T1/20 , G06F1/26 , G06F1/3203 , G06F1/324 , G06F1/325 , G06F1/3287 , G09G5/36 , G09G2360/08 , Y02D10/126 , Y02D10/171 , Y02D50/20
摘要： Power gating a portion of a graphics processor may be used to improve performance or to achieve a power budget. A processor granularity, such as a slice or subslice, may be gated.
摘要翻译：功率选通图形处理器的一部分可以用于提高性能或实现功率预算。可以选择处理器粒度，例如片或子片。

9. 发明授权

US10025367B2 Dynamic scaling of graphics processor execution resources 有权
公开(公告)号：US10025367B2
公开(公告)日：2018-07-17
申请号：US14463573
申请日：2014-08-19
申请人： Nikos Kaburlasos , Eric Samson
发明人： Nikos Kaburlasos , Eric Samson
IPC分类号： G06F1/32
摘要： In one embodiment execution units, graphics cores, or graphics sub-cores can be dynamically scaled across a frame of graphics operations. Available execution units within each graphics core may be scaled using utilization metrics such as the current utilization rate of the execution units and the submission of new draw calls. In one embodiment, one of more of the sub-cores within each graphics core may be enable or disabled based on current or past utilization of the sub-cores based on a set of current graphics operations.

10. 发明授权

US08209480B2 DRAM selective self refresh 有权
标题翻译： DRAM选择性自刷新
公开(公告)号：US08209480B2
公开(公告)日：2012-06-26
申请号：US12835525
申请日：2010-07-13
申请人： Nikos Kaburlasos , Jim Kardaeh
发明人： Nikos Kaburlasos , Jim Kardaeh
IPC分类号： G06F12/02
CPC分类号： G06F12/0292 , G11C11/406 , G11C11/40615 , G11C2211/4067 , Y02D10/13
摘要： In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associated with a second communication device, logic to establish a communication connection between the electronic apparatus and the first communication device, and logic to initiate, in the electronic apparatus, a connection request for a communication connection between the first communication device and the second communication device. Other embodiments may be described.
摘要翻译：在一些实施例中，电子设备包括通信接口，输入/输出接口，处理器和在电子设备中收集与第一通信设备相关联的第一标识符和与第二通信设备相关联的第二标识符的逻辑，在电子设备和第一通信设备之间建立通信连接的逻辑，以及在电子设备中启动第一通信设备和第二通信设备之间的通信连接的连接请求的逻辑。可以描述其他实施例。

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