专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4367465A Graphics light pen and method for raster scan CRT 失效
标题翻译：图形光笔和光栅扫描方法
公开(公告)号：US4367465A
公开(公告)日：1983-01-04
申请号：US137103
申请日：1980-04-04
申请人： Nicholas P. Mati , Frederick J. Porter , Robert W. Fredrickson
发明人： Nicholas P. Mati , Frederick J. Porter , Robert W. Fredrickson
IPC分类号： G06F3/023 , G06F3/033 , G06F3/037 , G06F3/038 , G06F3/048 , G06F3/153 , G09G1/16
CPC分类号： G06F3/037 , G06F3/0383 , G06F3/04892
摘要： A graphics system for a raster scan CRT implements a light pen tracked by a cursor. Hits corresponding to the cursor are distinguished from those corresponding to background data by a selective interlacing technique. A threshold level shifting technique providing accurate measurement of a horizontal component of the cursor allows accurate prediction of the location of the center of the field of view during the next frame.
摘要翻译：用于光栅扫描CRT的图形系统实现由光标跟踪的光笔。通过选择性隔行扫描技术将对应于游标的命中与对应于背景数据的命中区分开。提供对光标的水平分量的精确测量的阈值电平移位技术允许在下一帧期间精确地预测视场中心的位置。

2. 发明申请

US20100162085A1 Solid-state storage device including a high resolution analog-to-digital converter 有权
标题翻译：固态存储设备包括高分辨率模数转换器
公开(公告)号：US20100162085A1
公开(公告)日：2010-06-24
申请号：US12339842
申请日：2008-12-19
申请人： Nicholas P. Mati
发明人： Nicholas P. Mati
IPC分类号： H03M13/05 , G11C29/04 , G06F11/10 , G06F12/00 , H03M1/34
CPC分类号： G11C29/52 , G11C16/3418 , G11C27/005 , G11C29/50 , G11C2211/5641
摘要： A storage device includes a solid-state storage medium having a plurality of cells adapted to store data and an analog-to-digital converter (ADC) coupled to at least one cell of the plurality of cells. The ADC includes a first operating mode having a first number of quantization levels to determine a value stored in the at least one cell based on a number of possible values represented by the at least one cell. The ADC further includes a second operating mode having a second number of quantization levels to determine the value stored in the at least one cell, where the second number of quantization levels is greater than the first number of quantization levels. The ADC selectively enables the first or the second operating mode as a selected operating mode and determines a signal representative of the value stored in the at least one cell using the selected operating mode.
摘要翻译：存储设备包括具有适于存储数据的多个单元的固态存储介质和耦合到所述多个单元中的至少一个单元的模拟 - 数字转换器（ADC）。 ADC包括具有第一数量的量化级的第一操作模式，以基于由所述至少一个单元表示的可能值的数量来确定存储在所述至少一个单元中的值。 ADC还包括具有第二数量的量化级的第二操作模式，以确定存储在至少一个单元中的值，其中第二数量级的量化级大于第一数量级的量化级。 ADC选择性地使第一或第二操作模式作为所选择的操作模式，并且使用所选择的操作模式确定表示存储在所述至少一个单元中的值的信号。

3. 发明授权

US09449719B2 Solid-state storage device including a high resolution analog-to-digital converter 有权
标题翻译：固态存储设备包括高分辨率模数转换器
公开(公告)号：US09449719B2
公开(公告)日：2016-09-20
申请号：US12339842
申请日：2008-12-19
申请人： Nicholas P. Mati
发明人： Nicholas P. Mati
IPC分类号： H03M13/05 , H03M13/00 , G11C29/04 , G06F11/10 , G11C29/52 , G11C27/00 , G11C29/50 , G11C16/34
CPC分类号： G11C29/52 , G11C16/3418 , G11C27/005 , G11C29/50 , G11C2211/5641
摘要： A storage device includes a solid-state storage medium having a plurality of cells adapted to store data and an analog-to-digital converter (ADC) coupled to at least one cell of the plurality of cells. The ADC includes a first operating mode having a first number of quantization levels to determine a value stored in the at least one cell based on a number of possible values represented by the at least one cell. The ADC further includes a second operating mode having a second number of quantization levels to determine the value stored in the at least one cell, where the second number of quantization levels is greater than the first number of quantization levels. The ADC selectively enables the first or the second operating mode as a selected operating mode and determines a signal representative of the value stored in the at least one cell using the selected operating mode.
摘要翻译：存储设备包括具有适于存储数据的多个单元的固态存储介质和耦合到所述多个单元中的至少一个单元的模拟 - 数字转换器（ADC）。 ADC包括具有第一数量的量化级的第一操作模式，以基于由所述至少一个单元表示的可能值的数量来确定存储在所述至少一个单元中的值。 ADC还包括具有第二数量的量化级的第二操作模式，以确定存储在至少一个单元中的值，其中第二数量级的量化级大于第一数量级的量化级。 ADC选择性地使第一或第二操作模式作为所选择的操作模式，并且使用所选择的操作模式确定表示存储在所述至少一个单元中的值的信号。

4. 发明授权

US06239627B1 Clock multiplier using nonoverlapping clock pulses for waveform generation 失效
标题翻译：使用非重叠时钟脉冲的时钟乘法器用于波形生成
公开(公告)号：US06239627B1
公开(公告)日：2001-05-29
申请号：US08919702
申请日：1997-08-28
申请人： Andrew T. Brown , Nicholas P. Mati
发明人： Andrew T. Brown , Nicholas P. Mati
IPC分类号： H03B1900
CPC分类号： H03L7/0814 , H03K5/133 , H03L7/089
摘要： An improved clock generator performs clock multiplication using selectable generation of clock edges. A clock multiplier divides an input clock period into N edges by generating N non-overlapping clock pulses synchronized to the period of the reference clock—these edges are selectably combined to produce an output clock with the desired multiplication and duty cycle. The sequence of non-overlapping pulses is synchronized to the period of the input reference clock, i.e., to the first harmonic of the reference clock. A pulse generator network includes N pulse generators PG1-PGN, with the output of each pulse generator being coupled to the input of the next pulse generator. When triggered, each pulse generator generates a pulse P with a leading edge and a trailing edge, and a pulse width determined by a selectable pulse-width delay signal. The pulse generator PG1 is triggered by a leading edge of the reference clock, and the remaining pulse generators PG2-PGN are triggered by the trailing edge of the pulse P from the previous pulse generator. A synchronization circuit detects phase deviations between the trailing edge of the pulse PN from pulse generator PGN and the leading edge of the reference clock, and provides a corresponding phase adjustment signal used to adjust the pulse-width delay signal for at least one of the pulses P so as to achieve phase locking.
摘要翻译：改进的时钟发生器使用可选择的时钟边沿生成来执行时钟倍增。时钟乘法器通过产生与参考时钟的周期同步的N个非重叠时钟脉冲将输入时钟周期划分成N个边沿 - 这些边可选地组合以产生具有所需乘法和占空比的输出时钟。非重叠脉冲的序列与输入参考时钟的周期即基准时钟的一次谐波同步。脉冲发生器网络包括N个脉冲发生器PG1-PGN，每个脉冲发生器的输出端耦合到下一个脉冲发生器的输入端。当触发时，每个脉冲发生器产生具有前沿和后沿的脉冲P，以及由可选择的脉冲宽度延迟信号确定的脉冲宽度。脉冲发生器PG1由参考时钟的前沿触发，剩余的脉冲发生器PG2-PGN由前一个脉冲发生器的脉冲P的后沿触发。同步电路检测来自脉冲发生器PGN的脉冲PN的后沿与参考时钟的前沿之间的相位偏差，并且提供用于调整至少一个脉冲的脉冲宽度延迟信号的相应的相位调整信号 P，以实现相位锁定。

5. 发明授权

US5146461A Memory error correction system distributed on a high performance multiprocessor bus and method therefor 失效
标题翻译：内存纠错系统分布在高性能多处理器总线上及其方法
公开(公告)号：US5146461A
公开(公告)日：1992-09-08
申请号：US455640
申请日：1989-12-22
申请人： Douglas E. Duschatko , Nicholas P. Mati , Richard A. Herrington
发明人： Douglas E. Duschatko , Nicholas P. Mati , Richard A. Herrington
IPC分类号： G06F11/10
CPC分类号： G06F11/1044
摘要： A distributed error correction circuit for a synchronous high performance multiprocessor bus wherein the memory directly transfers data containing error fields to the multiprocessor bus without performing an error check. Each device, such as a plurality of processors or input/output busses, connected to the multiprocessor bus has error correction circuitry located between the multiprocessor bus and the device to perform error correction while the data is being transferred off the multiprocessor bus and stored in data buffers at the bandwidth of the multiprocessor bus. The error correction circuit detects and corrects data errors caused by the memory or the multiprocessor bus. The stored data is later transferred out of the buffers at the bandwidth of the device. Data from a device is delivered into the device buffers at the bandwidth of the device for later delivery of the data into memory at the bandwidth of the multiprocessor bus. During such transfers, the error correction circuitry generates the error field as the device data is transferred onto the multiprocessor bus.
摘要翻译：一种用于同步高性能多处理器总线的分布式纠错电路，其中存储器直接将包含错误字段的数据传送到多处理器总线，而不执行错误检查。连接到多处理器总线的每个设备（诸如多个处理器或输入/输出总线）具有位于多处理器总线和设备之间的纠错电路，以在数据从多处理器总线传送并且存储在数据中时进行纠错缓冲区在多处理器总线的带宽。纠错电路检测并纠正由存储器或多处理器总线引起的数据错误。存储的数据稍后在设备的带宽上从缓冲区中传出。来自设备的数据以设备的带宽传送到设备缓冲器中，以便在多处理器总线的带宽下将数据传送到存储器中。在这种传输期间，当设备数据被传送到多处理器总线上时，纠错电路产生错误字段。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式