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1. 发明授权

US08799737B1 Soft-information modification in concatenated decoding systems 有权
标题翻译：级联解码系统中的软信息修改
公开(公告)号：US08799737B1
公开(公告)日：2014-08-05
申请号：US13370354
申请日：2012-02-10
申请人： Nedeljko Varnica , Gregory Burd
发明人： Nedeljko Varnica , Gregory Burd
IPC分类号： H03M13/00
CPC分类号： H03M13/658 , H03M13/1111 , H03M13/4138 , H03M13/6331
摘要： Systems, methods, and other embodiments associated with data decoding are described. According to one embodiment, a method includes receiving an output value from one of a first block and a second block that form a pair of concatenated decoding blocks. The method includes determining a value of a modification criteria and modifying the output value based, at least in part, on the value of the modification criteria to form a modified output value. The modified output value is input to one of the first and second decoding blocks.
摘要翻译：描述与数据解码相关联的系统，方法和其他实施例。根据一个实施例，一种方法包括从形成一对级联解码块的第一块和第二块中的一个接收输出值。该方法包括至少部分地基于修改标准的值来确定修改标准的值并修改输出值，以形成修改的输出值。修改的输出值被输入到第一和第二解码块之一。

2. 发明授权

US08683277B1 Defect detection using pattern matching on detected data 有权
标题翻译：检测数据使用模式匹配进行缺陷检测
公开(公告)号：US08683277B1
公开(公告)日：2014-03-25
申请号：US13180723
申请日：2011-07-12
申请人： Nedeljko Varnica , Gregory Burd
发明人： Nedeljko Varnica , Gregory Burd
IPC分类号： G11C29/00 , G01R31/28 , G06F11/00
CPC分类号： G11C29/38 , G11B20/1889
摘要： Systems and methods for detection of defects on a magnetic storage medium. The method comprises: (1) receiving incoming detected data generated by reading information recorded on a storage medium, (2) identifying the defects in the storage medium based on comparison between the incoming detected data and a data pattern wherein the data pattern is predetermined; and (3) storing location information indicative of locations of the defects on the storage medium.
摘要翻译：用于检测磁存储介质上的缺陷的系统和方法。该方法包括：（1）接收通过读取记录在存储介质上的信息产生的输入检测数据，（2）基于输入的检测数据与数据模式预先确定的数据模式之间的比较识别存储介质中的缺陷; 和（3）将指示缺陷位置的位置信息存储在存储介质上。

3. 发明授权

US08683274B1 Error correction coding for varying signal-to-noise ratio channels 有权
标题翻译：改变信噪比通道的纠错编码
公开(公告)号：US08683274B1
公开(公告)日：2014-03-25
申请号：US13179429
申请日：2011-07-08
申请人： Nedeljko Varnica , Gregory Burd , Zining Wu
发明人： Nedeljko Varnica , Gregory Burd , Zining Wu
IPC分类号： G06F11/00
CPC分类号： H03M13/1148 , H03M13/033 , H03M13/1102 , H03M13/353
摘要： An ERSEC system that applies a level of error correction that is inversely related to susceptibility to error as indicated by a signal-to-noise ratio (SNR) profile of a channel. The SNR profile is estimated, detected or retrieved from an external source. The ERSEC system is used with any channel for which the SNRs can vary spatially, temporally or both.
摘要翻译： ERSEC系统，其应用与通道的信噪比（SNR）轮廓所指示的与误差易感性成反比关系的纠错水平。从外部源估计，检测或检索SNR分布。 ERSEC系统与任何可以在空间上，时间上或两者上变化的信道一起使用。

4. 发明授权

US08533496B1 Power management of iterative data processing systems 失效
标题翻译：迭代数据处理系统的电源管理
公开(公告)号：US08533496B1
公开(公告)日：2013-09-10
申请号：US12917097
申请日：2010-11-01
申请人： Nedeljko Varnica , Gregory Burd
发明人： Nedeljko Varnica , Gregory Burd
IPC分类号： G06F1/26 , G06F1/32 , G06F11/30
CPC分类号： G06F1/26 , G06F11/3024 , G06F11/3062 , H01L23/34 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) includes a decoding module configured to decode information units by performing T or less decoding iterations on each of the information units, where a maximum value of T is R, and where T is an integer greater than or equal to 1, and R is an integer greater than or equal to T. An iteration control module is configured to adjust a value of T based on a condition of the IC.
摘要翻译：集成电路（IC）包括：解码模块，被配置为通过对每个信息单元执行T或更少的解码迭代来解码信息单元，其中T的最大值为R，并且其中T是大于或等于1的整数并且R是大于或等于T的整数。迭代控制模块被配置为基于IC的条件来调整T的值。

5. 发明授权

US08489977B2 Low-density parity check codes for holographic storage 有权
标题翻译：用于全息存储的低密度奇偶校验码
公开(公告)号：US08489977B2
公开(公告)日：2013-07-16
申请号：US13475848
申请日：2012-05-18
申请人： Nedeljko Varnica , Seo-How Low , Gregory Burd , Zining Wu
发明人： Nedeljko Varnica , Seo-How Low , Gregory Burd , Zining Wu
IPC分类号： G06F11/10 , G06F11/30
CPC分类号： H03M13/116 , G11B20/1833 , G11B2020/185 , G11B2220/2504 , G11B2220/2508 , H03M13/036 , H03M13/6516
摘要： Systems and methods for constructing low-density parity check codes for holographic storage are provided. The methods include selecting parameters of a low-density parity check code, determining the number of bit processing elements and the amount of memory in an accompanying decoder, and constructing a mother matrix representation of a quasi-cyclic parity check matrix. The low-density parity check codes are optimized for performance, memory considerations, and throughput.
摘要翻译：提供了构建用于全息存储的低密度奇偶校验码的系统和方法。所述方法包括选择低密度奇偶校验码的参数，确定伴随的解码器中的比特处理元素的数量和存储量，以及构造准循环奇偶校验矩阵的母矩阵表示。针对性能，内存考虑和吞吐量优化了低密度奇偶校验码。

6. 发明授权

US08438461B2 Power consumption in LDPC decoder for low-power applications 有权
公开(公告)号：US08438461B2
公开(公告)日：2013-05-07
申请号：US12892183
申请日：2010-09-28
申请人： Nedeljko Varnica , Gregory Burd
发明人： Nedeljko Varnica , Gregory Burd
IPC分类号： H03M13/00
CPC分类号： H03M13/13 , H03M13/112 , H03M13/1128 , H03M13/114 , H03M13/116 , H03M13/3715 , H03M13/6502 , H04L1/0051 , H04L1/0053 , H04L1/0057
摘要： This disclosure relates generally to low power data decoding, and more particularly to low power iterative decoders for data encoded with a low-density parity check (LDPC) encoder. Systems and methods are disclosed in which a low-power syndrome check may be performed in the first iteration or part of the first iteration during the process of decoding a LDPC code in an LDPC decoder. Systems and methods are also disclosed in which a control over the precision of messages sent or received and/or a change in the scaling of these messages may be implemented in the LDPC decoder. The low-power techniques described herein may reduce power consumption without a substantial decrease in performance of the applications that make use of LDPC codes or the devices that make use of low-power LDPC decoders.

7. 发明授权

US08219878B1 Post-processing decoder of LDPC codes for improved error floors 有权
标题翻译： LDPC码的后处理解码器，用于改进错误层
公开(公告)号：US08219878B1
公开(公告)日：2012-07-10
申请号：US12327627
申请日：2008-12-03
申请人： Nedeljko Varnica , Gregory Burd , Zining Wu
发明人： Nedeljko Varnica , Gregory Burd , Zining Wu
IPC分类号： G06F11/00
CPC分类号： H03M13/1111 , H03M13/1142
摘要： Systems and methods are provided for decoding received codewords using an LDPC code. An LDPC post-processor is disclosed for performing post-processing when standard LDPC decoding fails due to a trapping set. The LDPC post-processor may direct the LDPC decoder to decode the received codeword again, but may change some of the inputs to the LDPC decoder so that the LDPC decoder does not fail in the same way. In one embodiment, the LDPC post-processor may modify the symbol positions in the received codeword that correspond to a particular unsatisfied check. In another embodiment, the LDPC post-processor may modify the messages in the decoder's iterative message algorithm that correspond to the symbol positions.
摘要翻译：提供了使用LDPC码对接收到的码字进行解码的系统和方法。公开了一种用于在标准LDPC解码由于陷阱集合而失败时执行后处理的LDPC后处理器。 LDPC后处理器可以引导LDPC解码器再次对接收的码字进行解码，但是可以将LDPC解码器的一些输入改变为使得LDPC解码器不以相同的方式失效。在一个实施例中，LDPC后处理器可以修改对应于特定不满足检查的接收码字中的符号位置。在另一个实施例中，LDPC后处理器可以修改对应于符号位置的解码器的迭代消息算法中的消息。

8. 发明申请

US20090150746A1 ITERATIVE DECODER SYSTEMS AND METHODS 有权
标题翻译：迭代解码器系统和方法
公开(公告)号：US20090150746A1
公开(公告)日：2009-06-11
申请号：US12329581
申请日：2008-12-06
申请人： Panu Chaichanavong , Nedeljko Varnica , Nitin Nangare , Gregory Burd , Zining Wu
发明人： Panu Chaichanavong , Nedeljko Varnica , Nitin Nangare , Gregory Burd , Zining Wu
IPC分类号： H03M13/05 , G06F11/07
CPC分类号： H03M13/41 , G11B20/1426 , G11B20/1803 , G11B2020/10759 , G11B2020/1457 , H03M13/09 , H03M13/1105 , H03M13/1111 , H03M13/1114 , H03M13/13 , H03M13/29 , H03M13/2948 , H03M13/3746 , H03M13/4146 , H03M13/6343 , H03M13/6502 , H03M13/6561
摘要： Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. This may allow for a 1/(1+D) precoder that may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.
摘要翻译：提供了系统和方法，用于改进迭代解码器系统的设计和性能。在一些实施例中，迭代解码器可以通过FIR RAM从FIR样本去耦，从而导致较不复杂的设计和较短的处理时间。在一些实施例中，当在迭代解码器的SOVA和LDPC之间传递信息时，可以使用中间存储器。在一些实施例中，可以在每次LDPC迭代期间从从LDPC接收的信息中连续序列化所需的SOVA信息。在一些实施例中，HR RLL编码器的1 /（1 + D2）预编码器可以被分成两个串行，1 /（1 + D）个预编码器。一个1 /（1 + D）预编码器可以被拉出HR RLL编码器外部并与迭代解码器结合使用。这可以允许可以与迭代解码器一起使用的1 /（1 + D）预编码器，同时保持由HR RLL编码器对编码信息施加的RLL约束。

9. 发明授权

US08989252B1 Methods and apparatus for power efficient iterative equalization 有权
标题翻译：用于功率有效迭代均衡的方法和装置
公开(公告)号：US08989252B1
公开(公告)日：2015-03-24
申请号：US13354256
申请日：2012-01-19
申请人： Nedeljko Varnica , Gregory Burd
发明人： Nedeljko Varnica , Gregory Burd
IPC分类号： H03H7/30
CPC分类号： H04L25/03318
摘要： Systems and methods for power efficient iterative equalization on a channel are provided. An iterative decoder decodes received data from a channel detector using a decoding process. The decoder computes a decision metric based on the decoded data and adjusts the number of iterations of the decoding process based on the decision metric. The adjustment occurs prior to a reliability criterion for the decoded data being satisfied. The decoder may pass control back to the channel detector if the adjusted number of iterations has occurred or if the reliability criterion is satisfied. Adjusting the number of iterations of the decoding process may include increasing the number of iterations from a predetermined number of iterations. The decision metric may be based on syndrome weight or hard decisions. The decision metric may be chosen to reduce average power consumption of the detector, the decoder, or circuitry including the detector and the decoder.
摘要翻译：提供了一种用于通道上的功率有效迭代均衡的系统和方法。迭代解码器使用解码过程对来自信道检测器的接收数据进行解码。解码器基于解码数据来计算决策度量，并根据决策度量来调整解码过程的迭代次数。在满足解码数据的可靠性标准之前进行调整。如果经过调整的迭代次数已经发生，或者如果可靠性标准被满足，则解码器可以将控制传递回信道检测器。调整解码过程的迭代次数可以包括从预定次数的迭代增加迭代次数。决策指标可以基于综合征重量或硬判断。可以选择决策度量以降低检测器，解码器或包括检测器和解码器的电路的平均功耗。

10. 发明授权

US08769380B1 Methods and apparatus for error recovery in memory systems employing iterative codes 有权
标题翻译：使用迭代代码的存储器系统中的错误恢复方法和装置
公开(公告)号：US08769380B1
公开(公告)日：2014-07-01
申请号：US13285723
申请日：2011-10-31
申请人： Gregory Burd , Nedeljko Varnica , Yifei Zhang , Nitin Nangare
发明人： Gregory Burd , Nedeljko Varnica , Yifei Zhang , Nitin Nangare
IPC分类号： H03M13/00 , H03M13/11 , H03M13/45 , H04L1/00
CPC分类号： H03M13/1128 , H03M13/1105 , H03M13/1142 , H03M13/152 , H03M13/2906 , H03M13/3707 , H03M13/3715 , H03M13/3723 , H03M13/4138 , H03M13/458 , H03M13/6331 , H04L1/0042 , H04L1/0051 , H04L1/0057
摘要： Systems and methods for error recovery are presented. Data is decoded with an iterative decoding scheme having a first set of parameters. In response to a determination that the iterative decoding scheme has failed, the data is re-read. While the data is being re-read, the iterative decoding scheme is reconfigured with a second set of parameters, and the data is decoded with the reconfigured iterative decoding scheme. In response to determination that the reconfigured iterative decoding scheme has failed, an error type associated with the data is determined. An error recovery scheme is selected from a plurality of error recovery schemes for the data based on the determined error type.
摘要翻译：介绍了错误恢复的系统和方法。用具有第一组参数的迭代解码方案对数据进行解码。响应于迭代解码方案失败的确定，重新读取数据。在重新读取数据的同时，使用第二组参数来重新配置迭代解码方案，并用重新配置的迭代解码方案对数据进行解码。响应于确定重新配置的迭代解码方案已经失败，确定与数据相关联的错误类型。基于所确定的错误类型，从用于数据的多个错误恢复方案中选择错误恢复方案。

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