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1. 发明申请

US20120254882A1 Controlling priority levels of pending threads awaiting processing 有权
标题翻译：控制待处理线程的优先级等待处理
公开(公告)号：US20120254882A1
公开(公告)日：2012-10-04
申请号：US13064598
申请日：2011-04-01
申请人： Nebojsa Makljenovic , Edvard Fielding , Andreas Due Engh-Halstvedt
发明人： Nebojsa Makljenovic , Edvard Fielding , Andreas Due Engh-Halstvedt
IPC分类号： G06F9/46
CPC分类号： G06F9/54 , G06F9/3851 , G06F9/3859 , G06F9/5011 , G06F2209/5021 , G06F2209/507
摘要： A data processing apparatus comprises processing circuitry arranged to process processing threads using resources accessible to the processing circuitry. A pipeline is provided for handling at least two pending threads awaiting processing by the processing circuitry. The pipeline includes at least one resource-requesting pipeline stage for requesting access to resources for the pending threads. A priority controller controls priority levels of the pending threads. The priority levels define a priority with which pending threads are granted access to resources. When a pending thread reaches a final pipeline stage, if the request resources are not yet available then the priority level of that thread is raised selectively and the thread is returned to a first pipeline stage of the pipeline. If the requested resources are available then the thread is forwarded from the pipeline.
摘要翻译：数据处理装置包括处理电路，其布置成使用处理电路可访问的资源来处理处理线程。提供管线用于处理待处理电路等待处理的至少两个待处理线程。流水线包括至少一个资源请求流水线级，用于请求访问待处理线程的资源。优先级控制器控制待处理线程的优先级。优先级定义优先级，通过该优先级等待线程授予对资源的访问权限。当待处理线程达到最终流水线阶段时，如果请求资源不可用，则该线程的优先级级别被有选择地提升，并且该线程返回到流水线的第一流水线级。如果所请求的资源可用，则线程将从管道转发。

2. 发明申请

US20120137076A1 Control of entry of program instructions to a fetch stage within a processing pipepline 有权
标题翻译：将程序指令输入到处理流水线内的提取阶段的控制
公开(公告)号：US20120137076A1
公开(公告)日：2012-05-31
申请号：US12926600
申请日：2010-11-29
申请人： Frode Heggelund , Rune Holm , Andreas Due Engh-Halstvedt , Edvard Fielding
发明人： Frode Heggelund , Rune Holm , Andreas Due Engh-Halstvedt , Edvard Fielding
IPC分类号： G06F12/08
CPC分类号： G06F12/0855 , G06F9/3802 , G06F9/3814
摘要： A processing pipeline 6, 8, 10, 12 is provided with a main query stage 20 and a fetch stage 22. A buffer 24 stores program instructions which have missed within a cache memory 14. Query generation circuitry within the main query stage 20 and within a buffer query stage 26 serve to concurrently generate a main query request and a buffer query request sent to the cache memory 14. The cache memory returns a main query response and a buffer query response. Arbitration circuitry 28 controls multiplexers 30, 32 and 34 to direct the program instruction at the main query stage 20, and the program instruction stored within the buffer 24 and the buffer query stage 26 to pass either to the fetch stage 22 or to the buffer 24. The multiplexer 30 can also select a new instruction to be passed to the main query stage 20.
摘要翻译：处理流水线6,8,10,12具有主查询级20和读取级22.缓冲器24存储已经错过高速缓冲存储器14内的程序指令。主查询级20内和内查询级内的查询生成电路缓冲器查询阶段26用于同时产生发送到高速缓存存储器14的主查询请求和缓冲查询请求。高速缓冲存储器返回主查询响应和缓冲查询响应。仲裁电路28控制多路复用器30,32和34以指导主查询阶段20处的程序指令，以及存储在缓冲器24和缓冲器查询阶段26内的程序指令，以通过读取级22或缓冲器24 复用器30还可以选择要传递到主查询级20的新指令。

3. 发明授权

US08589934B2 Controlling priority levels of pending threads awaiting processing 有权
标题翻译：控制待处理线程的优先级等待处理
公开(公告)号：US08589934B2
公开(公告)日：2013-11-19
申请号：US13064598
申请日：2011-04-01
申请人： Nebojsa Makljenovic , Edvard Fielding , Andreas Engh-Halstvedt
发明人： Nebojsa Makljenovic , Edvard Fielding , Andreas Engh-Halstvedt
IPC分类号： G06F9/46
CPC分类号： G06F9/54 , G06F9/3851 , G06F9/3859 , G06F9/5011 , G06F2209/5021 , G06F2209/507
摘要： A data processing apparatus comprises processing circuitry arranged to process processing threads using resources accessible to the processing circuitry. A pipeline is provided for handling at least two pending threads awaiting processing by the processing circuitry. The pipeline includes at least one resource-requesting pipeline stage for requesting access to resources for the pending threads. A priority controller controls priority levels of the pending threads. The priority levels define a priority with which pending threads are granted access to resources. When a pending thread reaches a final pipeline stage, if the request resources are not yet available then the priority level of that thread is raised selectively and the thread is returned to a first pipeline stage of the pipeline. If the requested resources are available then the thread is forwarded from the pipeline.
摘要翻译：数据处理装置包括处理电路，其布置成使用处理电路可访问的资源来处理处理线程。提供管线用于处理待处理电路等待处理的至少两个待处理线程。流水线包括至少一个资源请求流水线级，用于请求访问待处理线程的资源。优先级控制器控制待处理线程的优先级。优先权级别定义优先级，通过该优先级等待线程授予对资源的访问权限。当待处理线程达到最终流水线阶段时，如果请求资源不可用，则该线程的优先级级别被有选择地提升，并且该线程返回到流水线的第一流水线级。如果所请求的资源可用，则线程将从管道转发。

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