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1. 发明申请

US20060255474A1 Packaging structure and method 审中-公开
公开(公告)号：US20060255474A1
公开(公告)日：2006-11-16
申请号：US11444894
申请日：2006-06-01
申请人： Nazir Ahmad , Young-Do Kweon , Samuel Tam , Kyung-Moon Kim , Rajendra Pendse
发明人： Nazir Ahmad , Young-Do Kweon , Samuel Tam , Kyung-Moon Kim , Rajendra Pendse
IPC分类号： H01L23/48 , H01L21/00
CPC分类号： H01L21/563 , H01L24/29 , H01L24/81 , H01L2224/10135 , H01L2224/1134 , H01L2224/13144 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/29111 , H01L2224/29144 , H01L2224/2919 , H01L2224/73203 , H01L2224/81139 , H01L2224/81203 , H01L2224/81801 , H01L2224/83102 , H01L2224/83191 , H01L2224/83194 , H01L2224/92125 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01058 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/07802 , H01L2924/181 , H01L2924/01028 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points. Also, a flip chip package is made by the method. In some embodiments the metallurgical connection includes an alloy of gold and tin at the interface between the bumps and the interconnect points.

2. 发明授权

US06737295B2 Chip scale package with flip chip interconnect 有权
标题翻译：芯片级封装，带倒装芯片互连
公开(公告)号：US06737295B2
公开(公告)日：2004-05-18
申请号：US10081491
申请日：2002-02-22
申请人： Rajendra Pendse , Nazir Ahmad , Andrea Chen , Kyung-Moon Kim , Young Do Kweon , Samuel Tam
发明人： Rajendra Pendse , Nazir Ahmad , Andrea Chen , Kyung-Moon Kim , Young Do Kweon , Samuel Tam
IPC分类号： H01L2144
CPC分类号： H01L21/563 , H01L23/3114 , H01L24/11 , H01L24/13 , H01L24/29 , H01L24/32 , H01L24/81 , H01L2224/11 , H01L2224/1134 , H01L2224/13 , H01L2224/13099 , H01L2224/13144 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81136 , H01L2224/8114 , H01L2224/81203 , H01L2224/81801 , H01L2224/8183 , H01L2224/83192 , H01L2224/83194 , H01L2924/00013 , H01L2924/01006 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/351 , H01L2924/00012 , H01L2924/00 , H01L2224/29099
摘要： A flip chip package is formed by a solid-state bond technique for connecting the input/output pads on the integrated circuit chip and the package substrate. The solid-state bond technique involves a direct mating of metal surfaces, and does not employ any particulate conductive material nor any melting or flow of any interconnecting material. Accordingly the connections can be formed at very fine geometries. In another aspect, the space between the surface of the integrated circuit chip and the subjacent surface of the package substrate is filled with a patterned adhesive structure, which consists of one or more adhesive materials that are deployed in a specified pattern in relation to the positions of the second level interconnections between the package and the printed circuit board.
摘要翻译：通过用于连接集成电路芯片上的输入/输出焊盘和封装衬底的固态键合技术来形成倒装芯片封装。固态键合技术涉及金属表面的直接配合，并且不使用任何颗粒状导电材料，也不使用任何互连材料的任何熔化或流动。因此，连接可以以非常精细的几何形状形成。在另一方面，集成电路芯片的表面与封装衬底的下表面之间的空间填充有图案化的粘合剂结构，其由一种或多种相对于位置的指定图案部署的粘合剂材料组成的封装和印刷电路板之间的第二级互连。

3. 发明申请

US20050221535A1 Method for making self-coplanarity bumping shape for flip chip 有权
标题翻译：用于倒装芯片的自相互碰撞形状的方法
公开(公告)号：US20050221535A1
公开(公告)日：2005-10-06
申请号：US11145247
申请日：2005-06-03
申请人： Young-Do Kweon , Rajendra Pendse , Nazir Ahmad , Kyung-Moon Kim
发明人： Young-Do Kweon , Rajendra Pendse , Nazir Ahmad , Kyung-Moon Kim
IPC分类号： H01L21/60 , H01L23/498 , H01L21/44 , H01L21/48 , H01L21/50 , H01L23/495
CPC分类号： H01L24/12 , H01L23/49816 , H01L24/11 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0401 , H01L2224/05567 , H01L2224/05624 , H01L2224/0603 , H01L2224/1134 , H01L2224/11831 , H01L2224/1184 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/14 , H01L2224/1403 , H01L2224/81801 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/351 , H01L2924/00014 , H01L2224/13099 , H01L2224/05552 , H01L2924/00
摘要： A stud bump structure for electrical interconnection between a pair of members includes a base portion, and a stem portion. The base portion is affixed to a pad or trace in one of the pair of members to be interconnected (such as an integrated circuit chip), and the stem end is configured to contact a metal pad on the other member (such as a printed circuit board) to complete the interconnect. According to the invention, the stem end is truncated to form a transverse plane, and the stem is more compliant than the base. Also, a method for forming a stud bump on a contact surface, includes forming a bump base portion on the surface, drawing out a generally conical tail from a top of the base, and truncating the tail to form a stem portion having a planar transverse top surface and having a length from the top of the base portion to the top surface. In some embodiments the tail portion, at least, of the stud bump is formed using a wire bonding tool. Also, a method for forming an interconnect between a first member and a second member of an electronic package includes providing one of the members with the stud bumps of the invention and then bringing the corresponding bumps and pads together in a bonding process, the compliance of the stems portions of the bumps accommodating the variance from coplanarity of the pad surfaces.
摘要翻译：用于一对构件之间的电互连的柱形凸块结构包括基部和杆部。基座部分固定在要互连的一对构件之一（例如集成电路芯片）中的垫或轨迹中，并且杆端构造成接触另一构件上的金属垫（例如印刷电路板）完成互连。根据本发明，杆端被截断以形成横向平面，并且杆比基座更顺从。此外，在接触表面上形成柱形凸块的方法包括在表面上形成凸起基部，从基部的顶部抽出大致圆锥形的尾部，并且使尾部截断以形成具有平面横向并且具有从基部的顶部到顶面的长度。在一些实施例中，至少螺柱凸块的尾部部分使用引线接合工具形成。此外，用于在电子封装的第一部件和第二部件之间形成互连的方法包括：使部件中的一个部件具有本发明的螺柱凸块，然后在相互粘接过程中将相应的凸块和焊盘接合在一起，凸块的杆部分容纳与焊盘表面的共面性的差异。

4. 发明申请

US20050218515A1 Self-coplanarity bumping shape for flip chip 有权
公开(公告)号：US20050218515A1
公开(公告)日：2005-10-06
申请号：US11145246
申请日：2005-06-03
申请人： Young-Do Kweon , Rajendra Pendse , Nazir Ahmad , Kyung-Moon Kim
发明人： Young-Do Kweon , Rajendra Pendse , Nazir Ahmad , Kyung-Moon Kim
IPC分类号： H01L21/60 , H01L23/498 , H01L23/495 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/12 , H01L23/49816 , H01L24/11 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0401 , H01L2224/05567 , H01L2224/05624 , H01L2224/0603 , H01L2224/1134 , H01L2224/11831 , H01L2224/1184 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/14 , H01L2224/1403 , H01L2224/81801 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/351 , H01L2924/00014 , H01L2224/13099 , H01L2224/05552 , H01L2924/00
摘要： A stud bump structure for electrical interconnection between a pair of members includes a base portion, and a stem portion. The base portion is affixed to a pad or trace in one of the pair of members to be interconnected (such as an integrated circuit chip), and the stem end is configured to contact a metal pad on the other member (such as a printed circuit board) to complete the interconnect. According to the invention, the stem end is truncated to form a transverse plane, and the stem is more compliant than the base. Also, a method for forming a stud bump on a contact surface, includes forming a bump base portion on the surface, drawing out a generally conical tail from a top of the base, and truncating the tail to form a stem portion having a planar transverse top surface and having a length from the top of the base portion to the top surface. In some embodiments the tail portion, at least, of the stud bump is formed using a wire bonding tool. Also, a method for forming an interconnect between a first member and a second member of an electronic package includes providing one of the members with the stud bumps of the invention and then bringing the corresponding bumps and pads together in a bonding process, the compliance of the stems portions of the bumps accommodating the variance from coplanarity of the pad surfaces.

5. 发明授权

US06940178B2 Self-coplanarity bumping shape for flip chip 有权
标题翻译：倒装芯片的自共形凸起形状
公开(公告)号：US06940178B2
公开(公告)日：2005-09-06
申请号：US10080384
申请日：2002-02-22
申请人： Young-Do Kweon , Rajendra Pendse , Nazir Ahmad , Kyung-Moon Kim
发明人： Young-Do Kweon , Rajendra Pendse , Nazir Ahmad , Kyung-Moon Kim
IPC分类号： H01L21/60 , H01L23/498 , H01L23/48
CPC分类号： H01L24/12 , H01L23/49816 , H01L24/11 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0401 , H01L2224/05567 , H01L2224/05624 , H01L2224/0603 , H01L2224/1134 , H01L2224/11831 , H01L2224/1184 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/14 , H01L2224/1403 , H01L2224/81801 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/351 , H01L2924/00014 , H01L2224/13099 , H01L2224/05552 , H01L2924/00
摘要： A stud bump structure for electrical interconnection between a pair of members includes a base portion, and a stem portion. The base portion is affixed to a pad or trace in one of the pair of members to be interconnected (such as an integrated circuit chip), and the stem end is configured to contact a metal pad on the other member (such as a printed circuit board) to complete the interconnect. According to the invention, the stem end is truncated to form a transverse plane, and the stem is more compliant than the base. Also, a method for forming a stud bump on a contact surface, includes forming a bump base portion on the surface, drawing out a generally conical tail from a top of the base, and truncating the tail to form a stem portion having a planar transverse top surface and having a length from the top of the base portion to the top surface. In some embodiments the tail portion, at least, of the stud bump is formed using a wire bonding tool. Also, a method for forming an interconnect between a first member and a second member of an electronic package includes providing one of the members with the stud bumps of the invention and then bringing the corresponding bumps and pads together in a bonding process, the compliance of the stems portions of the bumps accommodating the variance from coplanarity of the pad surfaces.
摘要翻译：用于一对构件之间的电互连的柱形凸块结构包括基部和杆部。基座部分固定在要互连的一对构件之一（例如集成电路芯片）中的垫或轨迹中，并且杆端构造成接触另一构件上的金属垫（例如印刷电路板）完成互连。根据本发明，杆端被截断以形成横向平面，并且杆比基座更顺从。此外，在接触表面上形成柱形凸块的方法包括在表面上形成凸起基部，从基部的顶部抽出大致圆锥形的尾部，并且使尾部截断以形成具有平面横向并且具有从基部的顶部到顶表面的长度。在一些实施例中，至少螺柱凸块的尾部部分使用引线接合工具形成。此外，用于在电子封装的第一部件和第二部件之间形成互连的方法包括：使部件中的一个部件具有本发明的螺柱凸块，然后在相互粘接过程中将相应的凸块和焊盘接合在一起，凸块的杆部分容纳与焊盘表面的共面性的差异。

6. 发明申请

US20050056944A1 Super-thin high speed flip chip package 审中-公开
标题翻译：超薄高速倒装芯片封装
公开(公告)号：US20050056944A1
公开(公告)日：2005-03-17
申请号：US10960893
申请日：2004-10-07
申请人： Rajendra Pendse , Samuel Tam
发明人： Rajendra Pendse , Samuel Tam
IPC分类号： H01L23/12 , H01L21/56 , H01L23/31 , H01L23/498 , H01L23/66 , H01L25/065 , H01L25/07 , H01L25/10 , H01L25/18 , H01L23/52
CPC分类号： H01L23/3128 , H01L21/563 , H01L23/49816 , H01L23/66 , H01L24/16 , H01L24/48 , H01L2223/6627 , H01L2224/05599 , H01L2224/16225 , H01L2224/32225 , H01L2224/45099 , H01L2224/48095 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/8383 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/181 , H01L2924/1903 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A chip package achieves miniaturization and excellent high-speed operation by employing flip chip interconnection between the die and the package substrate, and mounting the chip on the same side of the package substrate as the solder balls for the second level interconnection to the printed circuit board. Also, two-die packages have a first die attached to the same surface as the second level interconnect structures and connected using flip chip interconnection, and a second die connected to the opposite surface of the substrate and interconnected either by wire bonding or by flip chip interconnection.
摘要翻译：芯片封装通过在芯片和封装基板之间采用倒装芯片互连，并且将芯片安装在封装基板的与印刷电路板的第二级互连的焊球相同的一侧上，实现了小型化和优异的高速操作。此外，双管芯封装具有附接到与第二级互连结构相同的表面并且使用倒装芯片互连连接的第一管芯，以及连接到衬底的相对表面并通过引线接合或通过倒装芯片互连的第二管芯互连。

7. 发明申请

US20050098886A1 Flip chip interconnection pad layout 有权
标题翻译：倒装芯片互连焊盘布局
公开(公告)号：US20050098886A1
公开(公告)日：2005-05-12
申请号：US10983898
申请日：2004-11-08
申请人： Rajendra Pendse
发明人： Rajendra Pendse
IPC分类号： H01L21/60 , H01L23/498 , H01L23/50 , H01L23/48
CPC分类号： H01L23/50 , H01L23/49838 , H01L24/81 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/81801 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025
摘要： A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate arranged in a manner complementary to the die pad layout and the signal lines routed from the signal pads beneath the die edge away from the die footprint, and has the power and ground lines routed to vias beneath the die footprint. Also, a flip chip semiconductor package in which the flip chip interconnect pad layouts have the die signal pads situated in the marginal part of the die and the die power and ground pads arranged on the die surface inboard from the signal pads, and the corresponding package substrates have signal pads arranged in a manner complementary to the die pad layout and signal lines routed from the signal pads beneath the die edge away from the die footprint.
摘要翻译：倒装芯片互连焊盘布局将芯片信号焊盘布置在靠近裸片周边的裸片表面上，并且芯片功率和接地焊盘从信号焊盘上排列在芯片表面上; 并且具有以与芯片焊盘布局互补的方式布置的相应封装衬底上的信号焊盘，并且信号线从模具边缘下方的信号焊盘远离管芯封装路由，并且将电源和接地线路由到下面的通孔模具占地面积。此外，倒装芯片半导体封装，其中倒装芯片互连焊盘布局具有位于管芯的边缘部分中的管芯信号焊盘以及从信号焊盘排列在管芯表面上的管芯电源和接地焊盘以及相应的封装衬底具有以与芯片焊盘布局互补的方式布置的信号焊盘，并且信号线从模具边缘下方的信号焊盘路由远离管芯封装。

8. 发明申请

US20060255473A1 Flip chip interconnect solder mask 审中-公开
标题翻译：倒装芯片互连焊盘
公开(公告)号：US20060255473A1
公开(公告)日：2006-11-16
申请号：US11435555
申请日：2006-05-16
申请人： Rajendra Pendse
发明人： Rajendra Pendse
IPC分类号： H01L23/48 , H01L21/58
CPC分类号： H05K3/3452 , H01L21/4846 , H01L21/4853 , H01L24/10 , H01L24/11 , H01L24/13 , H01L24/81 , H01L2224/11 , H01L2224/11822 , H01L2224/13 , H01L2224/13099 , H01L2224/16237 , H01L2224/8121 , H01L2224/81815 , H01L2224/83192 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01033 , H01L2924/01046 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H05K2201/0989 , H05K2201/10674 , H01L2924/00 , H01L2224/0401
摘要： A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the remelt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection includes a substrate having the common opening that spans a plurality of circuit elements. Also, a flip chip package includes a substrate having a common opening that spans a plurality of circuit elements.
摘要翻译：用于倒装芯片互连的焊接掩模具有跨越多个电路元件的公共开口。焊接掩模允许在互连的重熔阶段期间焊料的限制，但是在焊接掩模图案化的通用设计规则中。此外，用于倒装芯片布线的基板包括具有跨越多个电路元件的公共开口的基板。此外，倒装芯片封装包括具有跨越多个电路元件的公共开口的基板。

9. 发明申请

US20060170093A1 Flip chip interconnection pad layout 有权
公开(公告)号：US20060170093A1
公开(公告)日：2006-08-03
申请号：US11372755
申请日：2006-03-10
申请人： Rajendra Pendse
发明人： Rajendra Pendse
IPC分类号： H01L23/52
CPC分类号： H01L23/50 , H01L23/49838 , H01L24/81 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/81801 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025
摘要： A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate arranged in a manner complementary to the die pad layout and the signal lines routed from the signal pads beneath the die edge away from the die footprint, and has the power and ground lines routed to vias beneath the die footprint. Also, a flip chip semiconductor package in which the flip chip interconnect pad layouts have the die signal pads situated in the marginal part of the die and the die power and ground pads arranged on the die surface inboard from the signal pads, and the corresponding package substrates have signal pads arranged in a manner complementary to the die pad layout and signal lines routed from the signal pads beneath the die edge away from the die footprint.

10. 发明申请

US20060163715A1 Flip chip interconnection pad layout 有权
公开(公告)号：US20060163715A1
公开(公告)日：2006-07-27
申请号：US11372989
申请日：2006-03-10
申请人： Rajendra Pendse
发明人： Rajendra Pendse
IPC分类号： H01L23/52
CPC分类号： H01L23/50 , H01L23/49838 , H01L24/81 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/81801 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025
摘要： A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate arranged in a manner complementary to the die pad layout and the signal lines routed from the signal pads beneath the die edge away from the die footprint, and has the power and ground lines routed to vias beneath the die footprint. Also, a flip chip semiconductor package in which the flip chip interconnect pad layouts have the die signal pads situated in the marginal part of the die and the die power and ground pads arranged on the die surface inboard from the signal pads, and the corresponding package substrates have signal pads arranged in a manner complementary to the die pad layout and signal lines routed from the signal pads beneath the die edge away from the die footprint.

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