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1. 发明申请

US20100293512A1 CHIP DESIGN AND FABRICATION METHOD OPTIMIZED FOR PROFIT 有权
标题翻译：芯片设计和优化方法优化
公开(公告)号：US20100293512A1
公开(公告)日：2010-11-18
申请号：US12467326
申请日：2009-05-18
申请人： Nathan Buck , Howard H. Chen , James P. Eckhardt , Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Susan K. Lichtensteiger , Chandramouli Visweswariah , Tad J. Wilder
发明人： Nathan Buck , Howard H. Chen , James P. Eckhardt , Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Susan K. Lichtensteiger , Chandramouli Visweswariah , Tad J. Wilder
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031
摘要： Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated. Based on this profit model, changes to the chip design can be made in order to optimize yield as a function of all of the diverse metrics (e.g., performance, power consumption, etc.) and further to maximize the profit potential of the resulting chips.
摘要翻译：公开了一种计算机实现的方法，用于设计芯片以优化不同仓中的产量部分作为多个不同度量的函数，并进一步最大化所得到的芯片仓的利润潜力。该方法分别计算联合概率分布（JPD），每个JPD是不同度量（例如，性能，功耗等）的函数。基于JPD，生成相应的收益率曲线。利润函数然后将所有这些度量（例如，绩效值，功耗值等）的值减小到公共利润分母（例如，指示可能与给定度量值相关联的利润的货币值）。更具体地说，利润函数，尤其是货币价值可用于将各种收益率曲线组合成基于利润的收益率曲线，从中可以产生利润模型。基于这种利润模型，可以对芯片设计进行改变，以便根据所有不同的指标（例如性能，功耗等）来优化产量，并进一步最大化所得芯片的利润潜力。

2. 发明授权

US08086988B2 Chip design and fabrication method optimized for profit 有权
标题翻译：芯片设计和制造方法优化利润
公开(公告)号：US08086988B2
公开(公告)日：2011-12-27
申请号：US12467326
申请日：2009-05-18
申请人： Nathan Buck , Howard H. Chen , James P. Eckhardt , Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Susan K. Lichtensteiger , Chandramouli Visweswariah , Tad J. Wilder
发明人： Nathan Buck , Howard H. Chen , James P. Eckhardt , Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Susan K. Lichtensteiger , Chandramouli Visweswariah , Tad J. Wilder
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031
摘要： Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated. Based on this profit model, changes to the chip design can be made in order to optimize yield as a function of all of the diverse metrics (e.g., performance, power consumption, etc.) and further to maximize the profit potential of the resulting chips.
摘要翻译：公开了一种计算机实现的方法，用于设计芯片以优化不同仓中的产量部分作为多个不同度量的函数，并进一步最大化所得到的芯片仓的利润潜力。该方法分别计算联合概率分布（JPD），每个JPD是不同度量（例如，性能，功耗等）的函数。基于JPD，生成相应的收益率曲线。利润函数然后将所有这些度量（例如，绩效值，功耗值等）的值减小到公共利润分母（例如，指示可能与给定度量值相关联的利润的货币值）。更具体地说，利润函数，尤其是货币价值可用于将各种收益率曲线组合成基于利润的收益率曲线，从中可以生成利润模型。基于这种利润模型，可以对芯片设计进行改变，以便根据所有不同的指标（例如性能，功耗等）来优化产量，并进一步最大化所得芯片的利润潜力。

3. 发明授权

US08560989B2 Statistical clock cycle computation 有权
标题翻译：统计时钟周期计算
公开(公告)号：US08560989B2
公开(公告)日：2013-10-15
申请号：US13311832
申请日：2011-12-06
申请人： Nathan Buck , Brian Dreibelbis , John P. Dubuque , Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Jeffrey G. Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Michael H. Wood , Vladimir Zolotov
发明人： Nathan Buck , Brian Dreibelbis , John P. Dubuque , Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Jeffrey G. Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Michael H. Wood , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/10 , G06F2217/62
摘要： Systems and methods for statistical clock cycle computation and closing timing of an integrated circuit design to a maximum clock cycle or period. The method includes loading a design and timing model for at least one circuit path of an integrated circuit or a region of the integrated circuit into a computing device. The method further includes performing a statistical static timing analysis (SSTA) of the at least one circuit path using the loaded design and timing model to obtain slack canonical data. The method further includes calculating a maximum circuit clock cycle for the integrated circuit or the specified region of the integrated circuit in linear canonical form based upon the slack canonical data obtained from the SSTA.
摘要翻译：将集成电路设计的统计时钟周期计算和闭合时序的系统和方法设计到最大时钟周期或周期。该方法包括将用于集成电路或集成电路的区域的至少一个电路路径的设计和定时模型加载到计算设备中。该方法还包括使用加载的设计和定时模型来执行至少一个电路路径的统计静态时序分析（SSTA），以获得松散的规范数据。该方法还包括基于从SSTA获得的松弛规范数据，以线性规范形式计算集成电路或集成电路的指定区域的最大电路时钟周期。

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