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    • 10. 发明授权
    • Performing statistical timing analysis with non-separable statistical and deterministic variations
    • 用不可分的统计和确定性变化进行统计时序分析
    • US08418107B2
    • 2013-04-09
    • US12943541
    • 2010-11-10
    • Jeffrey G HemmettDebjit SinhaNatesan VenkateswaranChandramouli VisweswariahVladimir Zolotov
    • Jeffrey G HemmettDebjit SinhaNatesan VenkateswaranChandramouli VisweswariahVladimir Zolotov
    • G06F9/455G06F17/50
    • G06F17/504G06F2217/10G06F2217/84
    • In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on at least a first process parameter that is deterministic and corner-based and a second process parameter that is statistical and non-separable with the first process parameter, and performing a single timing run using the timing quantity, wherein the single timing run produces arrival times, required arrival times, and timing slacks at outputs, latches, and circuit nodes of the integrated circuit chip. The computed arrival times, required arrival times, and timing slacks can be projected to a corner value of deterministic variations in order to obtain a statistical model of the delays and stews at the corresponding corner.
    • 在一个实施例中,本发明是用于以不可分的统计和确定性变化执行统计时序分析的方法和装置。 用于执行集成电路芯片的定时分析的方法的一个实施例包括计算芯片栅极和导线的延迟和压摆,其中所述延迟和压摆取决于至少一个确定性和基于角的第一工艺参数,以及第二工艺参数 其与第一过程参数是统计的且不可分离的,并且使用定时数量执行单个定时运行,其中单个定时运行产生到达时间,所需的到达时间和定时偏移在输出,锁存器和电路节点 集成电路芯片。 计算的到达时间,所需的到达时间和时间休息可以被计算为确定性变化的角落值,以便获得相应角落处的延迟和炖菜的统计模型。