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1. 发明授权

US5914522A Power semiconductor structure with lateral transistor driven by vertical transistor 失效
标题翻译：功率半导体结构，横向晶体管由垂直晶体管驱动
公开(公告)号：US5914522A
公开(公告)日：1999-06-22
申请号：US859024
申请日：1997-05-20
申请人： Natale Aiello , Davide Patti , Salvatore Leonardi , Salvatore Scaccianoce
发明人： Natale Aiello , Davide Patti , Salvatore Leonardi , Salvatore Scaccianoce
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8224 , H01L21/8228 , H01L21/8249 , H01L27/06 , H01L27/07 , H01L27/082 , H01L29/732 , H01L29/00 , H01L27/102
CPC分类号： H01L27/0821 , H01L27/0722
摘要： A power semiconductor structure (200), in particular in VIPower technology, made from a chip of N-type semiconductor material (110), comprising a bipolar or field-effect vertical power transistor (125, 120, 110) having a collector or drain region in such N-type material (110); the semiconductor structure comprises a PNP bipolar lateral power transistor (210, 110, 220) having a base region in such N-type material (110) substantially in common with the collector or drain region of the vertical power transistor.
摘要翻译：一种功率半导体结构（200），特别是在VIPower技术中，由N型半导体材料（110）的芯片制成，包括具有集电极或漏极的双极或场效应垂直功率晶体管（125,120,110）这种N型材料（110）中的区域; 该半导体结构包括PNP双极侧向功率晶体管（210,110,220），其具有基本上与垂直功率晶体管的集电极或漏极区共同的N型材料（110）中的基极区域。

2. 发明授权

US06518139B1 Power semiconductor device structure with vertical PNP transistor 有权
标题翻译：功率半导体器件结构采用垂直PNP晶体管
公开(公告)号：US06518139B1
公开(公告)日：2003-02-11
申请号：US09569277
申请日：2000-05-11
申请人： Natale Aiello , Davide Patti , Salvatore Scaccianoce , Salvatore Leonardi
发明人： Natale Aiello , Davide Patti , Salvatore Scaccianoce , Salvatore Leonardi
IPC分类号： H01L218224
CPC分类号： H01L27/0821 , H01L21/8224
摘要： A power semiconductor device structure formed in a chip of semiconductor material includes an N-type substrate and an N-type epitaxial layer. The structure comprises a P-type insulation region which forms a pocket in which control circuitry is formed, and a plurality of fully insulated PNP power transistors. Each PNP power transistor comprises a P-type collector region including of a buried region between the substrate and the epitaxial layer and a contact region. The P region delimits a base N region within which an emitter P region is formed.
摘要翻译：形成在半导体材料芯片中的功率半导体器件结构包括N型衬底和N型外延层。该结构包括形成其中形成控制电路的口袋的P型绝缘区域和多个完全绝缘的PNP功率晶体管。每个PNP功率晶体管包括P型集电极区域，其包括在衬底和外延层之间的掩埋区域和接触区域。 P区域限定形成发射极P区域的基极N区域。

3. 发明授权

US06815798B2 Integrated capacitor for sensing the voltage applied to a terminal of an integrated or discrete power device on a semiconductor substrate 有权
标题翻译：用于感测施加到半导体衬底上的集成或分立功率器件的端子的电压的集成电容器
公开(公告)号：US06815798B2
公开(公告)日：2004-11-09
申请号：US10439277
申请日：2003-05-15
申请人： Natale Aiello , Davide Patti
发明人： Natale Aiello , Davide Patti
IPC分类号： H01L2900
CPC分类号： H01L27/0676 , H01L29/94
摘要： A capacitor for sensing a substrate voltage in an integrated circuit power device may be implemented by isolating a portion or segment of the metal layer that normally covers the heavily doped perimeter region typically used for electric field equalization. In conjunction, one or more portions of an isolation dielectric layer of silicon oxide are not removed from the surface of the semiconductor substrate, as is commonly done before depositing the metal layer. The portions of isolated silicon oxide which are not removed become the dielectric layer of the capacitor. Moreover, one plate of the capacitor is formed by the heavily doped perimeter region that is electrically connected to the substrate (e.g. a drain or collector region). The other plate is formed by the segment of metal isolated from the remaining metal layer defined directly over the heavily doped perimeter region.

4. 发明授权

US06441445B1 Integrated device with bipolar transistor and electronic switch in “emitter switching” configuration 有权
标题翻译：具有双极晶体管和电子开关的“发射极开关”配置的集成器件
公开(公告)号：US06441445B1
公开(公告)日：2002-08-27
申请号：US09413740
申请日：1999-10-06
申请人： Salvatore Leonardi , Davide Patti , Delfo Sanfilippo
发明人： Salvatore Leonardi , Davide Patti , Delfo Sanfilippo
IPC分类号： H01L2976
CPC分类号： H01L29/7802 , H01L21/823462
摘要： The integrated circuit device has a vertical conduction structure in which a region, which contains the base of a bipolar transistor, has zones having different concentrations. The concentrations are lower where the flow of charges is more intense and higher elsewhere. A high gain of the bipolar transistor and a low resistance of the electronic switch in conduction are thus obtained.
摘要翻译：集成电路器件具有垂直导电结构，其中包含双极晶体管的基极的区域具有不同浓度的区域。在电荷流动更强烈和其他地方较高的地方，浓度较低。因此获得双极晶体管的高增益和电子开关在导通中的低电阻。

5. 发明授权

US06297118B1 Vertical bipolar semiconductor power transistor with an interdigitzed geometry, with optimization of the base-to-emitter potential difference 有权
标题翻译：垂直双极半导体功率晶体管具有交叉的几何形状，优化了基极 - 发射极电位差
公开(公告)号：US06297118B1
公开(公告)日：2001-10-02
申请号：US09548784
申请日：2000-04-13
申请人： Davide Patti
发明人： Davide Patti
IPC分类号： H01L21331
CPC分类号： H01L29/66303 , H01L29/0804 , H01L29/7304
摘要： A transistor including an epitaxial layer with a first conductivity type, a base buried region with a second conductivity type, and a sinker base region with the second conductivity type which extends from a main surface of the transistor to the base buried region, and delimits, together with the base buried region, emitter fingers in the epitaxial layer. The transistor further includes an emitter buried region with the first conductivity type and a doping level which is higher than that of the epitaxial layer. The emitter buried region is embedded in the epitaxial layer in a position adjacent to the base buried region. A sinker emitter region having the first conductivity type and a doping level which is higher than that of the epitaxial layer and extends from the main surface to the emitter buried region inside the emitter fingers. The emitter buried region and the sinker emitter region delimit in each emitter finger pairs of sections which are mutually spaced and delimit between one another a central region of the epitaxial layer. The sinker emitter region of each pair of sections of an emitter finger extend in the vicinity of mutually facing edges of the emitter buried region of the pair of sections.
摘要翻译：一种晶体管，包括具有第一导电类型的外延层，具有第二导电类型的基极掩埋区域和具有第二导电类型的沉降片基极区域，从晶体管的主表面延伸到基底掩埋区域，与基极掩埋区一起，发射极指在外延层中。晶体管还包括具有第一导电类型的发射极掩埋区和高于外延层的掺杂水平的掺杂水平。发射极掩埋区域在与基底掩埋区域相邻的位置嵌入在外延层中。具有第一导电类型和掺杂水平的沉降弧发射极区域，其高于外延层的掺杂水平并且从发射极指状物内部的主表面延伸到发射极掩埋区域。发射极掩埋区域和沉陷弧发射极区域在每个发射极指状物中限定，这些区域彼此间隔开并且在彼此之间限定外延层的中心区域。发射极指的每对部分的沉降弧发射极区域在该对部分的发射极掩埋区域的相互面对的边缘附近延伸。

6. 发明授权

US05998855A Bipolar power transistor with buried base and interdigitated geometry 失效
标题翻译：双极功率晶体管，具有埋地和交叉几何形状
公开(公告)号：US05998855A
公开(公告)日：1999-12-07
申请号：US951686
申请日：1997-10-16
申请人： Davide Patti
发明人： Davide Patti
IPC分类号： H01L21/331 , H01L29/73 , H01L29/732 , H01L27/082 , H01L27/102 , H01L29/00 , H01L31/11
CPC分类号： H01L29/66303 , H01L29/7304
摘要： A bipolar power transistor of interdigitated geometry having a buried P type base region, a buried N type emitter region, a P type base-contact region, an N type emitter-contact region, connected to an emitter electrode and an N type connection region disposed around the emitter-contact region. The emitter region is buried within the base region in such a way that the buried emitter region and the connection region delimit a P type screen region. The transistor further includes a biasing P type region in contact with the emitter electrode, which extends up to the screen region.
摘要翻译：具有掩埋P型基极区域的埋入式几何形状的双极型功率晶体管，与发射电极连接的N型发射极区域，P型基极接触区域，N型发射极 - 接触区域和配置在N型连接区域中的N型发射极 - 围绕发射极 - 接触区域。发射极区域以埋地发射极区域和连接区域限定P型屏幕区域的方式埋在基极区域内。晶体管还包括与发射电极接触的偏置P型区域，其延伸到屏幕区域。

7. 发明授权

US08299579B2 Method for generating a signal representative of the current delivered to a load by a power device and relative power device 有权
标题翻译：用于产生表示由功率器件和相关功率器件传送到负载的电流的信号的方法
公开(公告)号：US08299579B2
公开(公告)日：2012-10-30
申请号：US13013513
申请日：2011-01-25
申请人： Davide Patti , Vincenzo Sciacca
发明人： Davide Patti , Vincenzo Sciacca
IPC分类号： H01L29/66
CPC分类号： H03K17/0828 , H03K17/567
摘要： An integrated power transistor includes emitter or source regions, and a comb-like patterned metal electrode structure interconnecting the emitter or source regions and defining at least one connection pad. The comb-like patterned metal electrode structure includes a plurality of fingers. A current sensing resistor produces a voltage drop representative of a current delivered to a load by the integrated power transistor. The current sensing resistor includes a portion of a current carrying metal track having a known resistance value and extending between one of the fingers and a connectable point along the current carrying metal track.
摘要翻译：集成功率晶体管包括发射极或源极区域以及将发射极或源极区域互连并限定至少一个连接焊盘的梳状图案化金属电极结构。梳状图案化的金属电极结构包括多个手指。电流感测电阻器产生代表由集成功率晶体管传送到负载的电流的电压降。电流感测电阻器包括具有已知电阻值的电流携带金属轨道的一部分，并且在手指之一和沿着载流金属轨道的可连接点之间延伸。

8. 发明申请

US20050051813A1 Monolithically integrated resistive structure with power IGBT (insulated gate bipolar transistor) devices 有权
标题翻译：具有功率IGBT（绝缘栅双极晶体管）器件的单片集成电阻结构
公开(公告)号：US20050051813A1
公开(公告)日：2005-03-10
申请号：US10888789
申请日：2004-07-09
申请人： Davide Patti , Antonino Torres
发明人： Davide Patti , Antonino Torres
IPC分类号： H01L29/739 , H01L29/78 , H01L29/80
CPC分类号： H01L29/7395
摘要： A device integrated in a semiconductor substrate of a first type of conductivity being crowned by a semiconductor layer of a second type of conductivity comprising a voltage controlled resistive structure and an IGBT device, wherein the resistive structure comprises at least one substantially annular region of the first type of conductivity which surrounds a portion of the semiconductor layer.
摘要翻译：一种集成在由第一导电类型的半导体衬底中的第一导电类型的半导体层的器件，其包括电压控制电阻结构和IGBT器件的第二导电类型的半导体层，其中所述电阻结构包括至少一个第一围绕半导体层的一部分的导电性的类型。

9. 发明授权

US06696916B2 Integrated vertical resistor structure with reduced dimensions, for high voltage, and manufacturing process thereof 有权
标题翻译：集成的垂直电阻器结构，具有减小的尺寸，用于高电压及其制造工艺
公开(公告)号：US06696916B2
公开(公告)日：2004-02-24
申请号：US09746373
申请日：2000-12-22
申请人： Delfo Sanfilippo , Davide Patti
发明人： Delfo Sanfilippo , Davide Patti
IPC分类号： H01C1012
CPC分类号： H01L28/20 , H01C7/1013 , H01C17/075 , H01L27/0802
摘要： The high-voltage resistor is of the vertical type, and is formed in a chip which includes a high-voltage region and a low-voltage region superimposed on the high-voltage region, both having a first conductivity type. An isolation region, at least partially buried, extends between the high-voltage region and the low-voltage region, and delimits a vertical resistive region connecting the high-voltage region to the low-voltage region.
摘要翻译：高压电阻器是垂直型的，并且形成在包括叠加在高电压区域上的高电压区域和低电压区域的芯片中，两者都具有第一导电类型。至少部分埋置的隔离区域在高电压区域和低压区域之间延伸，并且限定将高电压区域连接到低电压区域的垂直电阻区域。

10. 发明授权

US06696741B1 High breakdown voltage PN junction structure, and related manufacturing process 有权
标题翻译：高击穿电压PN结结构及相关制造工艺
公开(公告)号：US06696741B1
公开(公告)日：2004-02-24
申请号：US09443742
申请日：1999-11-19
申请人： Cesare Ronsisvalle , Piero Giorgio Fallica , Davide Patti
发明人： Cesare Ronsisvalle , Piero Giorgio Fallica , Davide Patti
IPC分类号： H01L2358
CPC分类号： H01L29/7802 , H01L21/762 , H01L29/0653
摘要： PN junction structure including a first junction region of a first conductivity type, and a second junction region of a second conductivity type, wherein between said first and second junction regions a grid of buried insulating material regions is provided.
摘要翻译： PN结结构，其包括第一导电类型的第一结区域和第二导电类型的第二结区域，其中在所述第一和第二接合区域之间提供掩埋绝缘材料区域格栅。

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