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1. 发明申请

US20090219750A1 NONVOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 审中-公开
标题翻译：非易失性存储器件及其控制方法
公开(公告)号：US20090219750A1
公开(公告)日：2009-09-03
申请号：US12394487
申请日：2009-02-27
申请人： Naoya TOKIWA , Hiroshi Maejima , Hideo Mukai
发明人： Naoya TOKIWA , Hiroshi Maejima , Hideo Mukai
IPC分类号： G11C11/00 , G11C7/00 , G11C8/00
CPC分类号： G11C17/12 , G11C5/02 , G11C8/08 , G11C8/14 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0028 , G11C13/0061 , G11C13/0069 , G11C2013/0092 , G11C2213/31 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistive element; a line selector circuit operative to decode an address signal to select the first and second lines; and a control circuit operative to execute control on at least one of data erase, write and read for the memory cell connected between the first and second lines selected at the line selector circuit. The control circuit executes control based on one parameter selected among a plurality of parameters. The line selector circuit specifies the parameter based on a first address portion in the address signal and selects the first and second lines based on a second address portion in the address signal.
摘要翻译：非易失性存储器件包括存储单元阵列，其包括第一和第二相交线以及布置在第一和第二线的交点处的电可擦除可编程存储单元，每个存储单元包含可变电阻元件; 行选择器电路，用于解码地址信号以选择第一和第二行; 以及控制电路，用于对连接在线选择器电路中选择的第一和第二线之间的存储单元的数据擦除，写入和读取中的至少一个执行控制。控制电路基于从多个参数中选择的一个参数来执行控制。线选择器电路基于地址信号中的第一地址部分来指定参数，并且基于地址信号中的第二地址部分选择第一和第二行。

2. 发明申请

US20110249498A1 THREE-DIMENSIONALLY STACKED NONVOLATILE SEMICONDUTOR MEMORY 有权
标题翻译：三维堆叠非易失性半导体存储器
公开(公告)号：US20110249498A1
公开(公告)日：2011-10-13
申请号：US13164938
申请日：2011-06-21
申请人： Naoya TOKIWA , Hideo Mukai
发明人： Naoya TOKIWA , Hideo Mukai
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C8/08 , G11C16/08 , G11C16/30 , G11C29/028 , G11C2029/1202 , H01L27/11578 , H01L27/11582
摘要： A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.
摘要翻译：本发明的一个方面的三维叠层的非易失性半导体存储器包括以彼此绝缘的方式堆叠在半导体衬底上的导电层，布置在层叠的导电层上的位线，半导体柱其延伸穿过堆叠的导电层，使用除了最上面和最下面的导电层之外的层叠的导电层并且具有板状平面形状的字线，设置在字线和半导体柱的交叉处的存储单元，具有提供适于每个字线的电位的信息的寄存器电路以及根据字线的输入地址信号读取保存在寄存器电路中的信息的电位控制电路，并提供适于对应于地址信号的字线。

3. 发明申请

US20100238706A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100238706A1
公开(公告)日：2010-09-23
申请号：US12708822
申请日：2010-02-19
申请人： Naoya TOKIWA , Hiroshi Maejima
发明人： Naoya TOKIWA , Hiroshi Maejima
IPC分类号： G11C11/00 , G11C8/00 , G11C7/00
CPC分类号： G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C2013/0085 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile semiconductor storage device includes a memory core that includes plural banks, the bank including plural memory cells and a data write circuit that supplies a bias voltage to the memory cell, the memory core being logically divided into plural pages, the page including a predetermined number of memory cells belonging to a predetermined number of banks; and a control circuit that controls the data write circuit to perform page write in each write unit including a predetermined number of memory cells, pieces of data being written in the page in the page write, the control circuit performing the page write by repeating a step including a program operation and a verify operation, the control circuit performing the program operation and the verify operation in a next step or later only to the write unit in which the data write is not completed in the verify operation.
摘要翻译：一种非易失性半导体存储装置，包括具有多个存储体的存储器芯，所述存储体包括多个存储单元，以及向所述存储单元提供偏置电压的数据写入电路，所述存储器核被逻辑地分割成多个页，所述页包括预定的属于预定数量的存储体的存储单元的数量; 以及控制电路，其控制所述数据写入电路，在包括预定数量的存储器单元的每个写入单元中执行页写入，所述多个数据被写入所述页写入中，所述控制电路通过重复步骤包括程序操作和验证操作，所述控制电路在下一步骤或稍后执行程序操作和验证操作仅在验证操作中仅写入数据写入的写入单元。

4. 发明申请

US20090154237A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090154237A1
公开(公告)日：2009-06-18
申请号：US12277698
申请日：2008-11-25
申请人： Naoya TOKIWA
发明人： Naoya TOKIWA
IPC分类号： G11C16/00 , G11C16/06 , G11C16/04 , G11C7/00
CPC分类号： G11C7/1078 , G11C7/109 , G11C16/20
摘要： A non-volatile semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a first register group configured to store control data used for controlling memory operations; an adjusting data storage area defined in the memory cell array so as to store adjusting data used for adjusting the control data; and a second register group configured to store the adjusting data read from the adjusting data storage area.
摘要翻译：非易失性半导体存储器件包括：具有布置在其中的电可重写和非易失性存储单元的存储单元阵列; 配置为存储用于控制存储器操作的控制数据的第一寄存器组; 在所述存储单元阵列中定义的调整数据存储区域，以存储用于调整所述控制数据的调整数据; 以及第二寄存器组，被配置为存储从调整数据存储区域读取的调整数据。

5. 发明申请

US20110069549A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE, NONVOLATILE SEMICONDUCTOR STORAGE SYSTEM AND METHOD OF MANAGING OF DEFECTIVE COLUMN IN NONVOLATILE SEMICONDUCTOR STORAGE SYSTEM 有权
标题翻译：非易失性半导体存储器件，非易失性半导体存储系统和非易失性半导体存储系统中缺陷管的管理方法
公开(公告)号：US20110069549A1
公开(公告)日：2011-03-24
申请号：US12957466
申请日：2010-12-01
申请人： Naoya TOKIWA
发明人： Naoya TOKIWA
IPC分类号： G11C16/06
CPC分类号： G11C16/06
摘要： A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit which takes out the data held in the first data holding circuit from the device, and a second data holding circuit in which data is automatically set at a time when power supply is turned on and in which the data is changeable based on a command input to the device, wherein the collective processing unit is equal to a sum of the number of units used within the device and the maximum number of units continuously output from the device to outside or input to the device from outside.
摘要翻译：公开了一种非易失性半导体存储装置，其包括其中布置非易失性存储器单元的存储单元阵列，暂时保持要同时从存储单元读取或写入存储单元的读或写数据的集合处理单元的第一数据保持电路，从设备取出保存在第一数据保持电路中的数据的电路，以及第二数据保持电路，其中在电源接通时自动设置数据，并且其中数据可基于命令输入到所述设备，其中所述集体处理单元等于在所述设备内使用的单元数量与从所述设备连续输出到所述设备的外部或从外部输入到所述设备的单元的最大数量之和。

6. 发明申请

US20130163329A1 MEMORY SYSTEM 审中-公开
标题翻译：记忆系统
公开(公告)号：US20130163329A1
公开(公告)日：2013-06-27
申请号：US13724898
申请日：2012-12-21
申请人： Naoya TOKIWA
发明人： Naoya TOKIWA
IPC分类号： G11C16/10 , G11C16/26
CPC分类号： G11C16/10 , G11C11/5642 , G11C11/5671 , G11C16/0483 , G11C16/26 , G11C2211/5641 , G11C2211/5646
摘要： Provided is a non-volatile semiconductor storage device according to one embodiment including: a memory cell array where memory cells capable of storing data of three or more levels are arrayed; a flag cell which is provided in an access prevention area where external access to the memory cell array is prevented; a flag data generating unit which generates flag data which is to be written in the flag cell based on a written state of the memory cell array; and an access prevention cancelling unit which permits external reading of the flag data based on an externally applied command.
摘要翻译：提供根据一个实施例的非易失性半导体存储装置，包括：存储单元阵列，其中能够存储三级或更多级别的数据的存储单元被排列; 提供在防止对存储单元阵列进行外部访问的访问防止区域中的标志单元; 标志数据生成单元，其基于所述存储单元阵列的写入状态生成要写入所述标志单元的标志数据; 以及访问防止消除单元，其允许基于外部施加的命令来对标志数据进行外部读取。

7. 发明申请

US20120195119A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120195119A1
公开(公告)日：2012-08-02
申请号：US13357241
申请日：2012-01-24
申请人： Yasushi NAGADOMI , Naoya TOKIWA
发明人： Yasushi NAGADOMI , Naoya TOKIWA
IPC分类号： G11C11/10 , G11C16/04
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/10 , G11C16/3454
摘要： In writing, a first write operation to a first memory cell is executed; and a second write operation for providing a first threshold-voltage distribution to a second memory cell adjacent to the first one, is executed. The first threshold voltage distribution is a lowest threshold-voltage distribution among the positive threshold voltage distributions. It is verified whether a desired threshold voltage distribution has been obtained in the first memory cell or not (first write verify operation), moreover, it is verified whether a first threshold voltage distribution or a threshold voltage distribution having a voltage level larger than the first threshold-voltage distribution has been obtained in the second memory cell or not (second write verify operation). A control circuit outputs results of the first write verify operation and the second write verify operation.
摘要翻译：在写入时，执行对第一存储单元的第一写入操作; 并且执行用于向与第一阈值电压分布相邻的第二存储单元提供第一阈值电压分布的第二写入操作。第一阈值电压分布是正阈值电压分布中的最低阈值电压分布。验证在第一存储器单元中是否已经获得期望的阈值电压分布（第一写入验证操作），此外，验证第一阈值电压分布或具有大于第一存储器单元的电压电平的阈值电压分布在第二存储器单元中已经获得阈值电压分布（第二写入验证操作）。控制电路输出第一写入验证操作和第二写入验证操作的结果。

8. 发明申请

US20120303871A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20120303871A1
公开(公告)日：2012-11-29
申请号：US13428089
申请日：2012-03-23
申请人： Naoya TOKIWA
发明人： Naoya TOKIWA
IPC分类号： G06F12/02
CPC分类号： G11C29/44 , G11C13/0004 , G11C13/0007 , G11C2029/4402
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array including a plurality of memory cells, a first register configured to store data of the memory cells, and a sequence control circuit configured to control the memory cell array and the first register. In at least a data read operation of the memory cells, the sequence control circuit reads out, from the memory cell array, data including flag information representing whether the number of failed bits is in an allowable range.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元阵列，该存储单元阵列包括多个存储器单元，第一寄存器，被配置为存储存储单元的数据;以及序列控制电路，被配置为控制存储单元阵列和第一寄存器。在存储器单元的至少一个数据读取操作中，顺序控制电路从存储单元阵列读出包括表示故障位数是否在允许范围内的标志信息的数据。

9. 发明申请

US20100202228A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE, NONVOLATILE SEMICONDUCTOR STORAGE SYSTEM AND METHOD OF MANAGING OF DEFECTIVE COLUMN IN NONVOLATILE SEMICONDUCTOR STORAGE SYSTEM 有权
标题翻译：非易失性半导体存储器件，非易失性半导体存储系统和非易失性半导体存储系统中缺陷管的管理方法
公开(公告)号：US20100202228A1
公开(公告)日：2010-08-12
申请号：US12767847
申请日：2010-04-27
申请人： Naoya TOKIWA
发明人： Naoya TOKIWA
IPC分类号： G11C29/04
CPC分类号： G11C16/06
摘要： A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit which takes out the data held in the first data holding circuit from the device, and a second data holding circuit in which data is automatically set at a time when power supply is turned on and in which the data is changeable based on a command input to the device, wherein the collective processing unit is equal to a sum of the number of units used within the device and the maximum number of units continuously output from the device to outside or input to the device from outside.
摘要翻译：公开了一种非易失性半导体存储装置，其包括其中布置非易失性存储器单元的存储单元阵列，暂时保持要同时从存储单元读取或写入存储单元的读或写数据的集合处理单元的第一数据保持电路，从设备取出保存在第一数据保持电路中的数据的电路，以及第二数据保持电路，其中在电源接通时自动设置数据，并且其中数据可基于命令输入到所述设备，其中所述集体处理单元等于在所述设备内使用的单元数量与从所述设备连续输出到所述设备的外部或从外部输入到所述设备的单元的最大数量之和。

10. 发明申请

US20100027341A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND NONVOLATILE SEMICONDUCTOR MEMORY SYSTEM 有权
标题翻译：非易失性半导体存储器件和非易失性半导体存储器系统
公开(公告)号：US20100027341A1
公开(公告)日：2010-02-04
申请号：US12533529
申请日：2009-07-31
申请人： Naoya TOKIWA , Shigeo OHSHIMA
发明人： Naoya TOKIWA , Shigeo OHSHIMA
IPC分类号： G11C16/04 , G11C16/06 , G11C5/14 , G11C7/10
CPC分类号： G11C16/30 , G11C5/143 , G11C5/145 , G11C8/06 , G11C8/10 , G11C16/0483
摘要： A memory may include word lines; bit lines; cells provided corresponding to intersections between the word lines and the bit lines; sense amplifiers detecting data; a column decoder selecting a certain bit line for the sense amplifiers to output read data or receive write data; a row decoder configured to select a certain word line; a charge pump supplying power to the sense amplifiers, the column decoder, and the row decoder; a logic circuit controlling the sense amplifiers, the column decoder, and the row decoder based on an address selecting the memory cells; a first power source input applying a voltage to the logic circuit; and a second power source input applying a voltage higher than a voltage of the first power source input to the charge pump, and to supply power to the charge pump at least at a data reading time and a data writing time.
摘要翻译：存储器可以包括字线; 位线对应于字线和位线之间的交点提供的单元; 感测放大器检测数据; 选择用于读出放大器的特定位线以输出读取数据或接收写入数据的列解码器; 行解码器，被配置为选择某个字线; 电荷泵向读出放大器，列解码器和行解码器供电; 基于选择存储器单元的地址来控制读出放大器，列解码器和行解码器的逻辑电路; 向逻辑电路施加电压的第一电源输入; 以及施加比所述第一电源输入的电压高于所述电荷泵的电压的第二电源输入，以及至少在数据读取时和数据写入时间向所述电荷泵供电。

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