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1. 发明授权

US07857946B2 Sputtering film forming method, electronic device manufacturing method, and sputtering system 有权
标题翻译：溅射成膜方法，电子器件制造方法和溅射系统
公开(公告)号：US07857946B2
公开(公告)日：2010-12-28
申请号：US12103813
申请日：2008-04-16
申请人： Naomu Kitano , Naoki Yamada , Takaaki Tsunoda , Nobuo Yamaguchi , Motomu Kosuda
发明人： Naomu Kitano , Naoki Yamada , Takaaki Tsunoda , Nobuo Yamaguchi , Motomu Kosuda
IPC分类号： C23C14/34
CPC分类号： C23C14/3464 , C23C14/16 , C23C14/505
摘要： A sputtering film forming method. which positions a target 4 and 5 at an incline to a surface of a substrate 10 whereupon a film is to be formed, and forms the film upon the surface of the substrate 10 whereupon the film is to be formed in an incline direction while the substrate 10 is rotated about a normal axis, terminates the forming of the film at a predetermined timing from the commencement of the forming of the film, wherein the forming of the film is terminated, when the substrate has rotated by 360 degrees×n+180 degrees+α, where n is a natural number, including 0, and −10 degrees
摘要翻译：溅射成膜方法。其将目标4和5以倾斜方式定位到基板10的表面，然后形成膜，并且在基板10的表面上形成膜，从而在斜面方向上形成膜，而基板 10相对于法线轴线旋转，从薄膜成型开始起的规定时间终止膜的成膜，其中，当基板旋转360度×n + 180度时，成膜为终止 +α，其中n是自然数，包括0和-10度<α<10度。

2. 发明申请

US20080264775A1 SPUTTERING FILM FORMING METHOD, ELECTRONIC DEVICE MANUFACTURING METHOD, AND SPUTTERING SYSTEM 有权
标题翻译：溅射膜成型方法，电子设备制造方法和溅射系统
公开(公告)号：US20080264775A1
公开(公告)日：2008-10-30
申请号：US12103813
申请日：2008-04-16
申请人： Naomu Kitano , Naoki Yamada , Takaaki Tsunoda , Nobuo Yamaguchi , Motomu Kosuda
发明人： Naomu Kitano , Naoki Yamada , Takaaki Tsunoda , Nobuo Yamaguchi , Motomu Kosuda
IPC分类号： C23C14/34
CPC分类号： C23C14/3464 , C23C14/16 , C23C14/505
摘要： A sputtering film forming method. which positions a target 4 and 5 at an incline to a surface of a substrate 10 whereupon a film is to be formed, and forms the film upon the surface of the substrate 10 whereupon the film is to be formed in an incline direction while the substrate 10 is rotated about a normal axis, terminates the forming of the film at a predetermined timing from the commencement of the forming of the film, wherein the forming of the film is terminated, when the substrate has rotated by 360 degrees×n+180 degrees+α, where n is a natural number, including 0, and −10 degrees
摘要翻译：溅射成膜方法。其将目标4和5以倾斜方式定位到基板10的表面，然后形成膜，并且在基板10的表面上形成膜，从而在斜面方向上形成膜，而基板 10绕着法线轴线旋转，从薄膜形成开始的预定时刻终止薄膜的成形，其中当薄膜旋转360度+ 180度+α时，薄膜的形成终止，其中n是自然数，包括0和-10度<α<10度。

3. 发明授权

US07655549B2 Method for depositing a metal gate on a high-k dielectric film 有权
标题翻译：在高k电介质膜上沉积金属栅极的方法
公开(公告)号：US07655549B2
公开(公告)日：2010-02-02
申请号：US11347256
申请日：2006-02-06
申请人： Wickramanayaka Sunil , Motomu Kosuda , Naoki Yamada , Naomu Kitano
发明人： Wickramanayaka Sunil , Motomu Kosuda , Naoki Yamada , Naomu Kitano
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/31 , H01L21/469
CPC分类号： H01L21/28185 , C23C14/5806 , H01L21/31645 , H01L21/67207 , H01L29/517 , Y10T29/41
摘要： A method to improve a high-k dielectric film and metal gate interface in the fabrication of a MOSFET by depositing a metal gate on a high-k dielectric, the method includes annealing a substrate with a high-k dielectric film deposited thereon in a thermal annealing module and depositing a metal gate material on the annealed substrate in a metal gate deposition module, wherein the annealing step and the depositing step are carried out consecutively without a vacuum break.
摘要翻译：一种通过在高k电介质上沉积金属栅极来改善MOSFET制造中的高k电介质膜和金属栅极界面的方法，该方法包括用沉积在其上的高k电介质膜对基片退火退火模块，并在金属栅极沉积模块中在退火的衬底上沉积金属栅极材料，其中退火步骤和沉积步骤连续执行而没有真空断裂。

4. 发明申请

US20090178621A1 SUBSTRATE TREATING SYSTEM FOR DEPOSITING A METAL GATE ON A HIGH-K DIELECTRIC FILM AND IMPROVING HIGH-K DIELECTRIC FILM AND METAL GATE INTERFACE 审中-公开
标题翻译：用于在高K电介质膜上沉积金属栅并改善高K介电膜和金属栅接口的基板处理系统
公开(公告)号：US20090178621A1
公开(公告)日：2009-07-16
申请号：US12400012
申请日：2009-03-09
申请人： Wickramanayaka Sunil , Motomu Kosuda , Naoki Yamada , Naomu Kitano
发明人： Wickramanayaka Sunil , Motomu Kosuda , Naoki Yamada , Naomu Kitano
IPC分类号： C23C16/54
CPC分类号： H01L21/28185 , C23C14/5806 , H01L21/31645 , H01L21/67207 , H01L29/517
摘要： An apparatus to improve high-k dielectric film and metal gate interface in the fabrication of MOSFET by depositing a metal gate on a high-k dielectric comprising an annealing step annealing a substrate with high-k dielectric film deposited thereon in a thermal annealing module and a depositing step depositing a metal gate material on said annealed substrate in a metal gate deposition module, characterized that said annealing step and depositing step are carried out consecutively without a vacuum break.
摘要翻译：一种通过在高k电介质上沉积金属栅极来改善MOSFET制造中的高k电介质膜和金属栅极界面的装置，包括退火步骤，在热退火模块中沉积有高k电介质膜的退火步骤退火基板，在金属栅极沉积模块中在所述退火的衬底上沉积金属栅极材料的沉积步骤，其特征在于，所述退火步骤和沉积步骤在没有真空断裂的情况下连续进行。

5. 发明申请

US20060194396A1 Method for depositing a metal gate on a high-k dielectric film and improving high-k dielectric film and metal gate interface, and a substrate treating system 有权
标题翻译：用于在高k电介质膜上沉积金属栅极并改善高k电介质膜和金属栅极界面的方法，以及基板处理系统
公开(公告)号：US20060194396A1
公开(公告)日：2006-08-31
申请号：US11347256
申请日：2006-02-06
申请人： Wickramanayaka Sunil , Motomu Kosuda , Naoki Yamada , Naomu Kitano
发明人： Wickramanayaka Sunil , Motomu Kosuda , Naoki Yamada , Naomu Kitano
IPC分类号： H01L21/336 , H01L21/00
CPC分类号： H01L21/28185 , C23C14/5806 , H01L21/31645 , H01L21/67207 , H01L29/517 , Y10T29/41
摘要： A method to improve a high-k dielectric film and metal gate interface in the fabrication of a MOSFET by depositing a metal gate on a high-k dielectric, the method includes annealing a substrate with a high-k dielectric film deposited thereon in a thermal annealing module and depositing a metal gate material on the annealed substrate in a metal gate deposition module, wherein the annealing step and the depositing step are carried out consecutively without a vacuum break.
摘要翻译：一种通过在高k电介质上沉积金属栅极来改善MOSFET制造中的高k电介质膜和金属栅极界面的方法，该方法包括用沉积在其上的高k电介质膜对基片退火退火模块，并在金属栅极沉积模块中在退火的衬底上沉积金属栅极材料，其中退火步骤和沉积步骤连续执行而没有真空断裂。

6. 发明申请

US20120043617A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120043617A1
公开(公告)日：2012-02-23
申请号：US13264955
申请日：2010-04-28
申请人： Takashi Nakagawa , Naomu Kitano , Kazuaki Matsuo , Motomu Kosuda , Toru Tatsumi
发明人： Takashi Nakagawa , Naomu Kitano , Kazuaki Matsuo , Motomu Kosuda , Toru Tatsumi
IPC分类号： H01L27/092 , H01L21/336
CPC分类号： H01L29/517 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/6659 , H01L29/7833
摘要： This invention provides a semiconductor device having a field effect transistor comprising agate electrode comprising a metal nitride layer and a polycrystalline silicon layer, and the gate electrode is excellent in thermal stability and realizes a desired work function.In the semiconductor device, a gate insulating film 6 on a silicon substrate 5 has a high-permittivity insulating film formed of a metal oxide, a metal silicate, a metal oxide introduced with nitrogen, or a metal silicate introduced with nitrogen, the gate electrode has a first metal nitride layer 7 provided on the gate insulating film 6 and containing Ti and N, a second metal nitride layer 8 containing Ti and N, and a polycrystalline silicon layer 9, in the first metal nitride layer 7, a molar ratio between Ti and N (N/Ti) is not less than 1.1, and a crystalline orientation X1 is 1.1
摘要翻译：本发明提供一种具有场效应晶体管的半导体器件，该场效应晶体管包括包含金属氮化物层和多晶硅层的玛瑙电极，并且该栅电极具有优异的热稳定性并实现所需的功函数。在半导体装置中，硅基板5上的栅极绝缘膜6具有由金属氧化物，金属硅酸盐，被引入氮的金属氧化物或导入氮的金属硅酸盐形成的高电容率绝缘膜，栅电极具有设置在栅极绝缘膜6上并且含有Ti和N的第一金属氮化物层7，含有Ti和N的第二金属氮化物层8和多晶硅层9在第一金属氮化物层7中的摩尔比 Ti和N（N / Ti）不小于1.1，结晶取向X1为1.1

7. 发明授权

US08026143B2 Semiconductor element and manufacturing method thereof 有权
标题翻译：半导体元件及其制造方法
公开(公告)号：US08026143B2
公开(公告)日：2011-09-27
申请号：US11933935
申请日：2007-11-01
申请人： Naomu Kitano , Takashi Minami , Motomu Kosuda , Heiji Watanabe
发明人： Naomu Kitano , Takashi Minami , Motomu Kosuda , Heiji Watanabe
IPC分类号： H01L21/336
CPC分类号： H01L29/517 , H01L21/28229 , H01L29/4966 , H01L29/513 , H01L29/78
摘要： The object of the present invention is to provide a method of manufacturing high permittivity gate dielectrics for a device such as an MOSFET. A HfSiO film is formed by sputtering a Hf metal film on a SiO2 film (or a SiON film) on a Si wafer. A TiO2 film is formed by sputtering a Ti metal film on the HfSiO film and subjecting the Ti metal film to a thermal oxidation treatment. A TiN metal film is deposited on the TiO2 film. The series of treatments are performed continuously, without exposing the films and the wafer to atmospheric air. The resultant TiN/TiO2/HfSiO/SiO2/Si structure satisfies the conditions: EOT
摘要翻译：本发明的目的是提供一种用于诸如MOSFET的器件的高介电常数栅极电介质的方法。通过在Si晶片上的SiO 2膜（或SiON膜）上溅射Hf金属膜来形成HfSiO膜。通过在HfSiO膜上溅射Ti金属膜并对Ti金属膜进行热氧化处理来形成TiO 2膜。在TiO 2膜上沉积TiN金属膜。连续进行一系列处理，而不会将膜和晶片暴露在大气中。所得TiN / TiO2 / HfSiO / SiO2 / Si结构满足条件：EOT <1.0nm，低漏电流和滞后<20mV。

8. 发明申请

US20100120238A1 SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD 有权
标题翻译：半导体制造设备和方法
公开(公告)号：US20100120238A1
公开(公告)日：2010-05-13
申请号：US12631286
申请日：2009-12-04
申请人： Naomu Kitano , Takashi Minami , Motomu Kosuda , Heiji Watanabe
发明人： Naomu Kitano , Takashi Minami , Motomu Kosuda , Heiji Watanabe
IPC分类号： H01L21/441 , C23C14/34 , C23C16/00
CPC分类号： H01L21/67207 , H01L21/28229 , H01L21/31683 , H01L29/513 , H01L29/517
摘要： A first aspect of the present invention provides a semiconductor manufacturing apparatus including: a load lock chamber; a transfer chamber; and a treatment chamber 1 and a treatment chamber 2 which carry out treatment using plasma, wherein, in the treatment chamber 2, an exhaust means is provided with a control means for making an oxygen partial pressure into 1*10−5 [Pa] or less. A second aspect of the present invention provides a method for forming a high dielectric constant film and a metal electrode successively, the method including the steps of: (1) depositing a metal film on a silicon oxide film or a silicon oxynitride film in the treatment chamber 1; (2) forming, in the treatment chamber 2, a high dielectric constant film by using the metal film formed in the treatment chamber 1; and (3) depositing, in the treatment chamber 1 or a treatment chamber 3 installed additionally, a metal electrode material on the high dielectric film formed in the treatment chamber 2, wherein the steps are carried out successively without being exposed to the atmosphere.
摘要翻译：本发明的第一方面提供一种半导体制造装置，包括：负载锁定室; 传送室; 以及处理室1和处理室2，其使用等离子体进行处理，其中在处理室2中，排气装置设置有用于使氧分压为1×10 -5 [Pa]或减。本发明的第二方面提供了一种依次形成高介电常数膜和金属电极的方法，所述方法包括以下步骤：（1）在处理中在氧化硅膜或氧氮化硅膜上沉积金属膜室1; （2）通过使用形成在处理室1中的金属膜在处理室2中形成高介电常数膜; （3）在处理室1或另外安装的处理室3内，在形成于处理室2中的高电介质膜上沉积金属电极材料，其中，这些步骤连续地进行而不暴露于大气中。

9. 发明授权

US08415753B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08415753B2
公开(公告)日：2013-04-09
申请号：US13264955
申请日：2010-04-28
申请人： Takashi Nakagawa , Naomu Kitano , Kazuaki Matsuo , Motomu Kosuda , Toru Tatsumi
发明人： Takashi Nakagawa , Naomu Kitano , Kazuaki Matsuo , Motomu Kosuda , Toru Tatsumi
IPC分类号： H01L27/092 , H01L21/336
CPC分类号： H01L29/517 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/6659 , H01L29/7833
摘要： This invention provides a semiconductor device having a field effect transistor comprising a gate electrode comprising a metal nitride layer and a polycrystalline silicon layer, and the gate electrode is excellent in thermal stability and realizes a desired work function. In the semiconductor device, a gate insulating film 6 on a silicon substrate 5 has a high-permittivity insulating film formed of a metal oxide, a metal silicate, a metal oxide introduced with nitrogen, or a metal silicate introduced with nitrogen, the gate electrode has a first metal nitride layer 7 provided on the gate insulating film 6 and containing Ti and N, a second metal nitride layer 8 containing Ti and N, and a polycrystalline silicon layer 9, in the first metal nitride layer 7, a molar ratio between Ti and N (N/Ti) is not less than 1.1, and a crystalline orientation X1 is 1.1
摘要翻译：本发明提供一种具有场效应晶体管的半导体器件，该场效应晶体管包括含有金属氮化物层和多晶硅层的栅电极，并且该栅电极具有优异的热稳定性并实现所需的功函数。在半导体装置中，硅基板5上的栅极绝缘膜6具有由金属氧化物，金属硅酸盐，被引入氮的金属氧化物或导入氮的金属硅酸盐形成的高电容率绝缘膜，栅电极具有设置在栅极绝缘膜6上并且含有Ti和N的第一金属氮化物层7，含有Ti和N的第二金属氮化物层8和多晶硅层9在第一金属氮化物层7中的摩尔比 Ti和N（N / Ti）不小于1.1，结晶取向X1为1.1

10. 发明授权

US08088678B2 Semiconductor manufacturing apparatus and method 有权
标题翻译：半导体制造装置及方法
公开(公告)号：US08088678B2
公开(公告)日：2012-01-03
申请号：US12631286
申请日：2009-12-04
申请人： Naomu Kitano , Takashi Minami , Motomu Kosuda , Heiji Watanabe
发明人： Naomu Kitano , Takashi Minami , Motomu Kosuda , Heiji Watanabe
IPC分类号： H01L32/05
CPC分类号： H01L21/67207 , H01L21/28229 , H01L21/31683 , H01L29/513 , H01L29/517
摘要： A first aspect of the present invention provides a semiconductor manufacturing apparatus including: a load lock chamber; a transfer chamber; and a treatment chamber 1 and a treatment chamber 2 which carry out treatment using plasma, wherein, in the treatment chamber 2, an exhaust means is provided with a control means for making an oxygen partial pressure into 1*10−5 [Pa] or less. A second aspect of the present invention provides a method for forming a high dielectric constant film and a metal electrode successively, the method including the steps of: (1) depositing a metal film on a silicon oxide film or a silicon oxynitride film in the treatment chamber 1; (2) forming, in the treatment chamber 2, a high dielectric constant film by using the metal film formed in the treatment chamber 1; and (3) depositing, in the treatment chamber 1 or a treatment chamber 3 installed additionally, a metal electrode material on the high dielectric film formed in the treatment chamber 2, wherein the steps are carried out successively without being exposed to the atmosphere.
摘要翻译：本发明的第一方面提供一种半导体制造装置，包括：负载锁定室; 传送室; 以及处理室1和处理室2，其使用等离子体进行处理，其中在处理室2中，排气装置设置有用于使氧分压为1×10 -5 [Pa]或减。本发明的第二方面提供了一种依次形成高介电常数膜和金属电极的方法，所述方法包括以下步骤：（1）在处理中在氧化硅膜或氧氮化硅膜上沉积金属膜室1; （2）通过使用形成在处理室1中的金属膜在处理室2中形成高介电常数膜; （3）在处理室1或另外安装的处理室3内，在形成于处理室2中的高电介质膜上沉积金属电极材料，其中，这些步骤连续地进行而不暴露于大气中。

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