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1. 发明授权

US07365529B2 Test structure design for reliability test 失效
标题翻译：可靠性测试的测试结构设计
公开(公告)号：US07365529B2
公开(公告)日：2008-04-29
申请号：US11465646
申请日：2006-08-18
申请人： Naomi Yoshida , Toshiyuki Nagata
发明人： Naomi Yoshida , Toshiyuki Nagata
IPC分类号： G01R31/28
CPC分类号： H01L22/34 , G01R31/2831 , G01R31/2853 , G01R31/2856 , H01L2924/0002 , H01L2924/00
摘要： A flexible semiconductor test structure that may be incorporated into a semiconductor device is provided. The test structure may include a plurality of test pads designed to physically stress conductive lines to which they are attached during thermal cycling. By utilizing test pads with different dimensions (lengths and/or widths), the effects of thermal stress generated by a plurality of conductive lines having corresponding different dimensions may be simulated.
摘要翻译：可以提供可并入半导体器件的柔性半导体测试结构。测试结构可以包括多个测试焊盘，其被设计成在热循环期间物理地应力它们所连接的导线。通过使用具有不同尺寸（长度和/或宽度）的测试垫，可以模拟由具有相应不同尺寸的多根导线产生的热应力的影响。

2. 发明申请

US20070013363A1 TEST STRUCTURE DESIGN FOR RELIABILITY TEST 失效
标题翻译：可靠性测试的测试结构设计
公开(公告)号：US20070013363A1
公开(公告)日：2007-01-18
申请号：US11465646
申请日：2006-08-18
申请人： Naomi Yoshida , Toshiyuki Nagata
发明人： Naomi Yoshida , Toshiyuki Nagata
IPC分类号： G01R31/28
CPC分类号： H01L22/34 , G01R31/2831 , G01R31/2853 , G01R31/2856 , H01L2924/0002 , H01L2924/00
摘要： A flexible semiconductor test structure that may be incorporated into a semiconductor device is provided. The test structure may include a plurality of test pads designed to physically stress conductive lines to which they are attached during thermal cycling. By utilizing test pads with different dimensions (lengths and/or widths), the effects of thermal stress generated by a plurality of conductive lines having corresponding different dimensions may be simulated.
摘要翻译：可以提供可并入半导体器件的柔性半导体测试结构。测试结构可以包括多个测试焊盘，其被设计成在热循环期间物理地应力它们所连接的导线。通过使用具有不同尺寸（长度和/或宽度）的测试垫，可以模拟由具有相应不同尺寸的多根导线产生的热应力的影响。

3. 发明授权

US07119571B2 Test structure design for reliability test 失效
标题翻译：可靠性测试的测试结构设计
公开(公告)号：US07119571B2
公开(公告)日：2006-10-10
申请号：US10997267
申请日：2004-11-24
申请人： Naomi Yoshida , Toshiyuki Nagata
发明人： Naomi Yoshida , Toshiyuki Nagata
IPC分类号： G01R31/26
CPC分类号： H01L22/34 , G01R31/2831 , G01R31/2853 , G01R31/2856 , H01L2924/0002 , H01L2924/00
摘要： A flexible semiconductor test structure that may be incorporated into a semiconductor device is provided. The test structure may include a plurality of test pads designed to physically stress conductive lines to which they are attached during thermal cycling. By utilizing test pads with different dimensions (lengths and/or widths), the effects of thermal stress generated by a plurality of conductive lines having corresponding different dimensions may be simulated.
摘要翻译：可以提供可并入半导体器件的柔性半导体测试结构。测试结构可以包括多个测试焊盘，其被设计成在热循环期间物理地应力它们所连接的导线。通过使用具有不同尺寸（长度和/或宽度）的测试垫，可以模拟由具有相应不同尺寸的多根导线产生的热应力的影响。

4. 发明申请

US20060109022A1 Test structure design for reliability test 失效
公开(公告)号：US20060109022A1
公开(公告)日：2006-05-25
申请号：US10997267
申请日：2004-11-24
申请人： Naomi Yoshida , Toshiyuki Nagata
发明人： Naomi Yoshida , Toshiyuki Nagata
IPC分类号： G01R31/26
CPC分类号： H01L22/34 , G01R31/2831 , G01R31/2853 , G01R31/2856 , H01L2924/0002 , H01L2924/00
摘要： A flexible semiconductor test structure that may be incorporated into a semiconductor device is provided. The test structure may include a plurality of test pads designed to physically stress conductive lines to which they are attached during thermal cycling. By utilizing test pads with different dimensions (lengths and/or widths), the effects of thermal stress generated by a plurality of conductive lines having corresponding different dimensions may be simulated.

5. 发明授权

US09589731B2 MEMS variable capacitor with enhanced RF performance 有权
标题翻译： MEMS可变电容器具有增强的RF性能
公开(公告)号：US09589731B2
公开(公告)日：2017-03-07
申请号：US14240654
申请日：2012-09-04
申请人： Robertus Petrus Van Kampen , Anartz Unamuno , Richard L. Knipe , Vikram Joshi , Roberto Gaddi , Toshiyuki Nagata
发明人： Robertus Petrus Van Kampen , Anartz Unamuno , Richard L. Knipe , Vikram Joshi , Roberto Gaddi , Toshiyuki Nagata
IPC分类号： H01G5/16 , H01G5/18 , B81B3/00 , B81C1/00
CPC分类号： H01G5/16 , B81B3/0051 , B81C1/00158 , B81C1/00476 , B81C1/00523 , H01G5/18
摘要： In a MEMS device, the manner in which the membrane lands over the RF electrode can affect device performance. Bumps or stoppers placed over the RF electrode can be used to control the landing of the membrane and thus, the capacitance of the MEMS device. The shape and location of the bumps or stoppers can be tailored to ensure proper landing of the membrane, even when over-voltage is applied. Additionally, bumps or stoppers may be applied on the membrane itself to control the landing of the membrane on the roof or top electrode of the MEMS device.
摘要翻译：在MEMS器件中，膜抵住RF电极的方式可能会影响器件性能。放置在RF电极上的撞击器或塞子可用于控制膜的着陆，从而控制MEMS器件的电容。可以调整凸块或塞子的形状和位置，以确保膜的适当着陆，即使施加过电压。此外，凸块或塞子可以施加在膜本身上以控制膜在MEMS装置的顶部或顶部电极上的着陆。

6. 发明申请

US20080108191A1 MEMORY DEVICE WITH SURFACE-CHANNEL PERIPHERAL TRANSISTORS 有权
标题翻译：具有表面通道外围晶体管的存储器件
公开(公告)号：US20080108191A1
公开(公告)日：2008-05-08
申请号：US11972048
申请日：2008-01-10
申请人： Toshiyuki Nagata
发明人： Toshiyuki Nagata
IPC分类号： H01L21/8242
CPC分类号： H01L27/10894 , H01L21/823807 , H01L21/823842 , H01L21/823892 , H01L27/1052 , H01L27/10817 , H01L27/10852 , H01L27/10897
摘要： A method of forming a memory device (e.g., a DRAM) including array and peripheral circuitry. A plurality of undoped polysilicon gates 58 are formed. These gates 58 are classed into three groups; namely, first conductivity type peripheral gates 58p, second conductivity type peripheral gates 58n, and array gates 58a. The array gates 58a and the first conductivity type peripheral gates 58n are masked such that the second conductivity type peripheral gates 58p remain unmasked. A plurality of second conductivity type peripheral transistors can then be formed by doping each of the second conductivity type peripheral gates 58p, while simultaneously doping a first and a second source/drain region 84 adjacent each of the second conductivity type peripheral gates 58p. The second conductivity type peripheral gates 58p are then masked such that the first conductivity type peripheral gates 58n remain unmasked. A plurality of first conductivity type peripheral transistors are formed by doping each of the first conductivity type peripheral gates 58n, while simultaneously doping a first and a second source/drain region 82 adjacent each of the first conductivity type peripheral gates 58n.
摘要翻译：一种形成包括阵列和外围电路的存储器件（例如，DRAM）的方法。形成多个未掺杂的多晶硅栅极58。这些门58分为三组; 即第一导电型外围栅极58p，第二导电型外围栅极58n和阵列栅极58a。阵列栅极58a和第一导电型外围栅极58n被掩蔽，使得第二导电型外围栅极58p保持未屏蔽。然后可以通过掺杂每个第二导电型外围栅极58 p来形成多个第二导电类型的外围晶体管，同时掺杂与第二导电型周边栅极58 p相邻的第一和第二源极/漏极区域84。然后对第二导电类型的外围栅极58 p进行掩模，使得第一导电型外围栅极58n保持未屏蔽。多个第一导电型外围晶体管通过掺杂每个第一导电类型的外围栅极58 n而形成，同时掺杂第一和第二源极/漏极区域82，其邻近于每个第一导电型周边栅极58 n。

7. 发明授权

US06486023B1 Memory device with surface-channel peripheral transistor 有权
标题翻译：具有表面通道外围晶体管的存储器件
公开(公告)号：US06486023B1
公开(公告)日：2002-11-26
申请号：US09178470
申请日：1998-10-23
申请人： Toshiyuki Nagata
发明人： Toshiyuki Nagata
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/823807 , H01L21/823842 , H01L21/823892 , H01L27/1052 , H01L27/10817 , H01L27/10852 , H01L27/10897
摘要： A method of forming a memory device (e.g., a DRAM) including array and peripheral circuitry. A plurality of undoped polysilicon gates 58 are formed. These gates 58 are classed into three groups; namely, first conductivity type peripheral gates 58p, second conductivity type peripheral gates 58n, and array gates 58a. The array gates 58a and the first conductivity type peripheral gates 58n are masked such that the second conductivity type peripheral gates 58p remain unmasked. A plurality of second conductivity type peripheral transistors can then be formed by doping each of the second conductivity type peripheral gates 58p, while simultaneously doping a first and a second source/drain region 84 adjacent each of the second conductivity type peripheral gates 58p. The second conductivity type peripheral gates 58p are then masked such that the first conductivity type peripheral gates 58n remain unmasked. A plurality of first conductivity type peripheral transistors are formed by doping each of the first conductivity type peripheral gates 58n, while simultaneously doping a first and a second source/drain region 82 adjacent each of the first conductivity type peripheral gates 58n.
摘要翻译：一种形成包括阵列和外围电路的存储器件（例如，DRAM）的方法。形成多个未掺杂的多晶硅栅极58。这些门58分为三组; 即第一导电型外围栅极58p，第二导电型外围栅极58n和阵列栅极58a。阵列栅极58a和第一导电型外围栅极58n被掩蔽，使得第二导电型外围栅极58p保持未屏蔽。然后可以通过掺杂每个第二导电类型的外围栅极58p来形成多个第二导电类型的外围晶体管，同时掺杂与第二导电型周边栅极58p相邻的第一和第二源极/漏极区域84。然后，第二导电型外围栅极58p被掩蔽，使得第一导电类型的外围栅极58n保持未屏蔽。通过掺杂第一导电型周边栅极58n中的每一个，同时掺杂与第一导电型周边栅极58n中的每一个相邻的第一和第二源极/漏极区域82，形成多个第一导电型外围晶体管。

8. 发明授权

US5317177A Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5317177A
公开(公告)日：1994-05-31
申请号：US889323
申请日：1992-05-27
申请人： Toshiyuki Nagata , Hiroyuki Yoshida , Takayuki Niuya , Yoshihiro Ogata , Katsushi Boku , Yoichi Miyai
发明人： Toshiyuki Nagata , Hiroyuki Yoshida , Takayuki Niuya , Yoshihiro Ogata , Katsushi Boku , Yoichi Miyai
IPC分类号： H01L21/205 , H01L21/265 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H01L29/68 , H01L29/78 , H01L29/92
CPC分类号： H01L27/10861 , H01L27/10829
摘要： A semiconductor device in which a trench-shaped groove (20) and a depression (100), which is formed by removing at least part of the area above and adjacent to the groove, are formed to be continuous on one side of the semiconductor substrate, in which aforementioned groove and aforementioned depression is buried a polysilicon conductive layer (103), the top of which conductive layer is converted into an insulator (102), the bottom of which insulating film (102) is contained in the depression (100). It is possible to form the element areas according to designs, and it is also possible to flatten the surface without wire cutting in the conductive layer.
摘要翻译：一种半导体器件，其中沟槽形沟槽（20）和凹陷（100）形成为在半导体衬底的一侧上是连续的其中上述凹槽和上述凹陷掩埋有多晶硅导电层（103），其导电层的顶部被转换成绝缘体（102），其绝缘膜（102）的底部包含在凹部（100）中，。可以根据设计形成元件区域，并且还可以在导电层中没有线切割的同时使表面变平。

9. 发明授权

US5804478A Method of forming a trench-type semiconductor memory device 失效
标题翻译：形成沟槽型半导体存储器件的方法
公开(公告)号：US5804478A
公开(公告)日：1998-09-08
申请号：US698433
申请日：1996-08-15
申请人： Toshiyuki Nagata , Hiroyuki Yoshida , Takayuki Niuya , Yoshihiro Ogata
发明人： Toshiyuki Nagata , Hiroyuki Yoshida , Takayuki Niuya , Yoshihiro Ogata
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10861 , H01L28/40
摘要： A type of semiconductor device with a configuration characterized by the fact that an electroconductive film (90) is formed beforehand in connection to step (54a) of insulating film(54), and an electroconductive layer (63) with step from the aforementioned electroconductive film is coated to form the side contact of the memory cell. Even in the case when breakage takes place in electroconductive layer (63), the electrical conduction is still maintained via electroconductive film (90), and no wire breakage, in effect, takes place. In addition, it is possible to form the pattern for the aforementioned electroconductive layer by, for instance, etching back method without applying a special mask; hence, the manufacturing process is simplified.
摘要翻译：一种具有这样的结构的半导体器件，其特征在于，预先连接到绝缘膜（54）的步骤（54a）形成导电膜（90），并且导电层（63）与上述导电膜被涂覆以形成存储单元的侧面接触。即使在导电层（63）中发生断裂的情况下，仍然通过导电膜（90）保持导电，实际上不发生断线。此外，可以通过例如在不施加特殊掩模的情况下回蚀刻方法来形成上述导电层的图案; 因此，简化了制造过程。

10. 发明授权

US5470777A Method of fabricating random access memory device having sidewall insulating layer on the laminate structure 失效
标题翻译：制造在层叠结构上具有侧壁绝缘层的随机存取存储器件的方法
公开(公告)号：US5470777A
公开(公告)日：1995-11-28
申请号：US248830
申请日：1994-05-25
申请人： Toshiyuki Nagata , Hiroyuki Yoshida , Takayuki Niuya
发明人： Toshiyuki Nagata , Hiroyuki Yoshida , Takayuki Niuya
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L27/00 , H01L21/70
CPC分类号： H01L21/768 , H01L27/10829 , H01L27/10861 , H01L27/10873
摘要： A semiconductor device in which a bit line (41), which is adhered to a contact hole (49) between polysilicon gate electrodes (35) and (36), is directly connected with an SiO.sub.2 film (53) having the same pattern on the gate electrodes; wherein an Si.sub.3 N.sub.4 layer (56) is buried outside the contact areas between the gate electrodes to approximately the same height as the SiO.sub.2 layer (53). The interlayer insulating film of the conventional memory cells array unit is no longer required, and it is not necessary to form contact holes in the interlayer insulating film. As a result, even if the gaps between the gates are designed to be small, there will be no short-circuiting between the bit line and word lines due to mask shifting, etc., making it possible to offer a highly integrated, highly reliable device.
摘要翻译：一种半导体器件，其中粘附到多晶硅栅电极（35）和（36）之间的接触孔（49）上的位线（41）与具有相同图案的SiO 2膜（53）直接连接栅电极; 其中Si 3 N 4层（56）被掩埋在栅电极之间的接触区域的外部，与SiO 2层（53）大致相同的高度。不再需要传统的存储单元阵列单元的层间绝缘膜，并且不需要在层间绝缘膜中形成接触孔。结果，即使栅极之间的间隙被设计为小，由于掩模移位等，位线和字线之间也不会发生短路，使得可以提供高集成度，高可靠性设备。

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