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1. 发明授权

US06339751B1 Circuit design support apparatus and a method 失效
标题翻译：电路设计支持设备及方法
公开(公告)号：US06339751B1
公开(公告)日：2002-01-15
申请号：US09153910
申请日：1998-09-16
申请人： Naomi Takeda , Shozo Isobe , Yuichiro Matsuoka , Masami Aihara , Seiichi Nishio
发明人： Naomi Takeda , Shozo Isobe , Yuichiro Matsuoka , Masami Aihara , Seiichi Nishio
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A circuit design support apparatus partially converts a description of a circuit model to simulate the circuit operation. A register signal replacement section replaces a register signal with a variable in a process related with the register signal of the description and inserts a declaration of the variable in the process instead of a declaration of the register signal in the description. A clock signal simplification section replaces a clock signal with a variable in a clock signal reference process of the description and unifies a clock signal update process to the clock signal reference process in the description.
摘要翻译：电路设计支持设备部分地转换电路模型的描述以模拟电路操作。寄存器信号替换部分用与描述的寄存器信号相关的处理中的变量替换寄存器信号，并且在描述中插入变量的声明而不是寄存器信号的声明。时钟信号简化部分用描述的时钟信号参考处理中的变量替换时钟信号，并将时钟信号更新处理与描述中的时钟信号参考处理相统一。

2. 发明授权

US4855726A Signal tracing apparatus for logic circuit diagrams 失效
标题翻译：用于逻辑电路图的信号跟踪装置
公开(公告)号：US4855726A
公开(公告)日：1989-08-08
申请号：US102494
申请日：1987-09-29
申请人： Seiichi Nishio
发明人： Seiichi Nishio
IPC分类号： G06F17/50 , G06T11/20
CPC分类号： G06T11/203
摘要： In a logic circuit diagram processing apparatus, when an original signal name or an original signal line is designated, all the signal lines associated with the designated signal (i.e. signal lines through which the designated signal is passed; logic elements to which the designated signal lines are connected; signal lines connected to the logic elements to which already-traced signal lines are connected, etc.) are displayed in color or colors, for instance, visually different from that of other signal lines, for providing an easy operator's visual confirmation or visual check of a logic circuit.
摘要翻译：在逻辑电路图处理装置中，当指定原始信号名称或原始信号线时，与指定信号相关联的所有信号线（即，指定信号通过的信号线;指定信号线的逻辑元件被连接到连接到已经跟踪的信号线连接的逻辑元件的信号线等）以颜色或颜色显示，例如与其他信号线的视觉上不同，以提供容易的操作者的视觉确认或目视检查逻辑电路。

3. 发明申请

US20070250303A1 DESIGN SUPPORT APPARATUS 审中-公开
标题翻译：设计支持设备
公开(公告)号：US20070250303A1
公开(公告)日：2007-10-25
申请号：US11736074
申请日：2007-04-17
申请人： Hiroshi Imai , Seiichi Nishio
发明人： Hiroshi Imai , Seiichi Nishio
IPC分类号： G06F9/45
CPC分类号： G06F17/505
摘要： A design support apparatus is for designing a logic circuit. The apparatus includes: a display device; an behavioral description storage section that stores behavioral description that describes functions of the logic circuit; a loop statement detection section that detects a loop statement that describes a repeat operation from the behavioral description; a loop statement analysis section that generates structure information that describes a structure of the loop statement by analyzing the loop statement detected by the loop statement detection section; and a display control section that controls the display device to display the structure information. The display control section controls the display device to display operations in a loop body defined by the loop statement in a time series manner.
摘要翻译：设计支持装置用于设计逻辑电路。该装置包括：显示装置; 行为描述存储部，其存储描述所述逻辑电路的功能的行为描述; 循环语句检测部分，其从行为描述中检测描述重复操作的循环语句; 循环语句分析部分，通过分析由循环语句检测部分检测到的循环语句，生成描述循环语句结构的结构信息; 以及控制显示装置显示结构信息的显示控制部。显示控制部分控制显示装置以时间序列方式在由循环语句定义的循环体中显示操作。

4. 发明授权

US06668363B2 Clock supplying circuit and method having enable buffer cells with first and second input terminals 失效
标题翻译：具有使能缓冲单元的第一和第二输入端的时钟供给电路和方法
公开(公告)号：US06668363B2
公开(公告)日：2003-12-23
申请号：US09875159
申请日：2001-06-07
申请人： Fumihiro Minami , Takeshi Kitahara , Kimiyoshi Usami , Seiichi Nishio
发明人： Fumihiro Minami , Takeshi Kitahara , Kimiyoshi Usami , Seiichi Nishio
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F2217/78
摘要： A computer aided design technique for clock gated logic circuits effective to reduce the electric power consumption is disclosed. The computer aided design for clock gated logic circuits is conducted by extracting, by the use of information about a clock gated logic circuit under the design, a halt condition under which a clocked circuit driven by a clock signal can halt with no clock signal supplied, generating enable signal candidates, from a halt condition, which can be used as enable signals in the clock gated logic circuit, analyzing the clock gated logic circuit in order to obtain information about a delay time of signal transmission and electric power consumption reduction if respective one of enable signal candidates is used as an enable signal of a clock gating circuit inserted in the clock gated logic circuit under the design, storing enable signal candidate information including the result of the analysis conducted by an analysis step in an information store, selecting an appropriate one of the enable signal candidates which satisfy given restrictions regarding a delay time of signal transmission in the clock gated logic circuit under the design, by the use of enable signal candidate information; and adding the clock gating circuit activated with the enable signal as selected by enable signal selection step to the clock gated logic circuit under the design.
摘要翻译：公开了一种有效降低功耗的时钟选通逻辑电路的计算机辅助设计技术。用于时钟门控逻辑电路的计算机辅助设计是通过使用设计下的时钟门控逻辑电路的信息来提取停止条件，在该停止条件下，由时钟信号驱动的时钟电路可以在没有提供时钟信号的情况下停止，从可以用作时钟选通逻辑电路中的使能信号的停止条件产生使能信号候选，分析时钟门控逻辑电路，以便获得关于信号传输的延迟时间和电力消耗减少的信息，如果相应的一个使能信号候选被用作在设计下插入时钟门控逻辑电路中的时钟门控电路的使能信号，存储包括通过信息存储中的分析步骤进行的分析结果的使能信号候选信息，选择适当的满足关于信号传输的延迟时间的给定限制的使能信号候选中的一个 e时钟门控逻辑电路设计，通过使用使能信号候补信息; 并将通过使能信号选择步骤选择的使能信号激活的时钟选通电路设计为时钟门控逻辑电路。

5. 发明授权

US06272667B1 Method and apparatus for clock gated logic circuits to reduce electric power consumption 失效
标题翻译：用于时钟门控逻辑电路的方法和装置，以减少电力消耗
公开(公告)号：US06272667B1
公开(公告)日：2001-08-07
申请号：US09168961
申请日：1998-10-09
申请人： Fumihiro Minami , Takeshi Kitahara , Kimiyoshi Usami , Seiichi Nishio
发明人： Fumihiro Minami , Takeshi Kitahara , Kimiyoshi Usami , Seiichi Nishio
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F2217/78
摘要： A computer aided design technique for clock gated logic circuits effective to reduce the electric power consumption is disclosed. The computer aided design for clock gated logic circuits is conducted by extracting, by the use of information about a clock gated logic circuit under the design, a halt condition under which a clocked circuit driven by a clock signal can halt with no clock signal supplied, generating enable signal candidates, from said halt condition, which can be used as enable signals in the clock gated logic circuit, analyzing the clock gated logic circuit in order to obtain information about a delay time of signal transmission and electric power consumption reduction if respective one of enable signal candidates is used as an enable signal of a clock gating circuit inserted in the clock gated logic circuit under the design, storing enable signal candidate information including the result of the analysis conducted by said analysis step in a information store means, selecting an appropriate one of the enable signal candidates which satisfy given restrictions regarding a delay time of signal transmission in the clock gated logic circuit under the design, by the use of said enable signal candidate information; and adding the clock gating circuit activated with the enable signal as selected by said enable signal selection step to the clock gated logic circuit under the design.
摘要翻译：公开了一种有效降低功耗的时钟选通逻辑电路的计算机辅助设计技术。用于时钟门控逻辑电路的计算机辅助设计是通过使用设计下的时钟选通逻辑电路的信息来提取停止条件，在该停止条件下，由时钟信号驱动的时钟电路可以在没有提供时钟信号的情况下停止，从所述停止条件产生使能信号候选，其可以用作时钟门控逻辑电路中的使能信号，分析时钟门控逻辑电路，以便获得关于信号传输的延迟时间和电力消耗减少的信息，如果相应的一个使能信号候选被用作在设计下插入时钟门控逻辑电路中的时钟门控电路的使能信号，将包括由所述分析步骤进行的分析的结果的使能信号候补信息存储在信息存储装置中，满足关于信号传输的延迟时间的给定限制的适当一个使能信号候选在时钟门控逻辑电路的设计下，通过使用所述使能信号候选信息; 并且将由所述使能信号选择步骤选择的使能信号激活的时钟选通电路加到设计时钟门控逻辑电路。

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