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1. 发明授权

US5248628A Method of fabricating a semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US5248628A
公开(公告)日：1993-09-28
申请号：US896537
申请日：1992-06-09
申请人： Naoko Okabe , Satoshi Inoue , Kazumasa Sunouchi , Takashi Yamada , Akihiro Nitayama , Hiroshi Takato
发明人： Naoko Okabe , Satoshi Inoue , Kazumasa Sunouchi , Takashi Yamada , Akihiro Nitayama , Hiroshi Takato
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10808
摘要： A semiconductor memory device wherein at least one of a storage node contact hole and a bit line contact hole includes a first contact hole made in a first inter-layer insulating film formed over a gate electrode and a second contact hole made in a second inter-layer insulating film formed over an electrically conductive material embedded up to a level higher than the gate electrode in the first contact hole which is contacted with the electrically conductive material, the conductive material being exposed by etching a part of the second inter-layer insulating film, whereby the size of the memory device can be made small and the reliability can be improved. Further, a capacitor is formed in a layer higher than a bit line thereby to facilitate the processing of a storage node electrode to increase the capacitor area and to improve the reliability since it is unnecessary to carry out patterning a plate electrode within a cell array. With the above construction, a short-circuiting between the embedded layers is removed and a good quality of the second inter-layer insulating film is formed.
摘要翻译：一种半导体存储器件，其中存储节点接触孔和位线接触孔中的至少一个包括在形成在栅电极上的第一层间绝缘膜中形成的第一接触孔和在第二互连孔中形成的第二接触孔，在导电材料上形成的层间绝缘膜，该导电材料在与导电材料接触的第一接触孔中嵌入高于栅电极的电平，通过蚀刻第二层间绝缘膜的一部分而露出导电材料从而可以使存储器件的尺寸小并且可以提高可靠性。此外，在高于位线的层中形成电容器，从而不需要对单元阵列内的平板电极进行图案化，便于存储节点电极的处理以增加电容器面积并提高可靠性。利用上述结构，去除了嵌入层之间的短路，形成了第二层间绝缘膜的良好质量。

2. 发明授权

US5144579A Semiconductor memory device and its fabricating method 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US5144579A
公开(公告)日：1992-09-01
申请号：US578608
申请日：1990-09-07
申请人： Naoko Okabe , Satoshi Inoue , Kazumasa Sunouchi , Takashi Yamada , Akihiro Nitayama , Hiroshi Takato
发明人： Naoko Okabe , Satoshi Inoue , Kazumasa Sunouchi , Takashi Yamada , Akihiro Nitayama , Hiroshi Takato
IPC分类号： H01L27/04 , H01L21/28 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10808
摘要： A semiconductor memory device wherein at least one of a storage node contact hole and a bit line contact hole includes a first contact hole made in a first inter-layer insulating film formed over a gate electrode and a second contact hole made in a second inter-layer insulating film formed over an electrically conductive material embedded up to a level higher than the gate electrode in the first contact hole which is contacted with the electrically conductive material, the conductive material being exposed by etching a part of the second inter-layer insulating film, whereby the size of the memory device can be made small and the reliability can be improved. Further, a capacitor is formed in a layer higher than a bit line thereby to facilitate the processing of a storage node electrode to increase the capacitor area and to improve the reliability since it is unnecessary to carry out patterning a plate electrode within a cell array. With the above construction, a short-circuiting between the embedded layers is removed and a good quality of the second inter-layer insulating film is formed.
摘要翻译：一种半导体存储器件，其中存储节点接触孔和位线接触孔中的至少一个包括在形成在栅电极上的第一层间绝缘膜中形成的第一接触孔和在第二互连孔中形成的第二接触孔，在导电材料上形成的层间绝缘膜，该导电材料在与导电材料接触的第一接触孔中嵌入高于栅电极的电平，通过蚀刻第二层间绝缘膜的一部分而露出导电材料从而可以使存储器件的尺寸小并且可以提高可靠性。此外，在高于位线的层中形成电容器，从而不需要对单元阵列内的平板电极进行图案化，便于存储节点电极的处理以增加电容器面积并提高可靠性。利用上述结构，去除了嵌入层之间的短路，形成了第二层间绝缘膜的良好质量。

3. 发明授权

US5488242A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5488242A
公开(公告)日：1996-01-30
申请号：US156931
申请日：1993-11-24
申请人： Kazumasa Sunouchi , Hiroshi Takato , Tohru Ozaki , Naoko Okabe , Katsuhiko Hieda , Fumio Horiguchi , Akihiro Nitayama , Takashi Yamada , Kouji Hasimoto , Satosi Inoue
发明人： Kazumasa Sunouchi , Hiroshi Takato , Tohru Ozaki , Naoko Okabe , Katsuhiko Hieda , Fumio Horiguchi , Akihiro Nitayama , Takashi Yamada , Kouji Hasimoto , Satosi Inoue
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78 , H01L27/02 , H01L29/68 , H01L29/92
CPC分类号： H01L27/10829
摘要： In a DRAM having a structure in which a storage node electrode is formed via an insulator film in a trench formed in a memory cell region to thereby form a capacitor, and in which the storage node electrode is connected in the source/drain regions of a MOSFET through a storage node contact formed in a part of the insulator film, the trench is disposed so as to deviate widthwise in a channel region of the MOSFET, so that the distance between adjacent element regions is reduced without causing misalignment of masks used in the formation of the storage node contact, thereby to provide a miniaturized high-reliability DRAM. In addition, the storage node contact and the trench can be formed in large size.
摘要翻译：在具有通过形成在存储单元区域中的沟槽中的绝缘膜形成存储节点电极从而形成电容器的结构的DRAM中，并且其中存储节点电极连接在源极/漏极区域 MOSFET通过形成在绝缘膜的一部分中的存储节点接触，沟槽设置成在MOSFET的沟道区域中宽度偏离，使得相邻元件区域之间的距离减小，而不会导致在形成存储节点接触，从而提供小型化的高可靠性DRAM。此外，存储节点接触和沟槽可以形成为大尺寸。

4. 发明授权

US5164801A A P channel MIS type semiconductor device 失效
标题翻译： P通道MIS型半导体器件
公开(公告)号：US5164801A
公开(公告)日：1992-11-17
申请号：US790066
申请日：1991-11-12
申请人： Katsuhiko Hieda , Kazumasa Sunouchi , Akihiro Nitayama , Kazushi Tsuda , Hiroshi Takato , Naoko Takenouchi
发明人： Katsuhiko Hieda , Kazumasa Sunouchi , Akihiro Nitayama , Kazushi Tsuda , Hiroshi Takato , Naoko Takenouchi
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/06 , H01L27/092 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/823864 , H01L27/0623 , H01L27/092 , H01L29/78 , Y10S257/90
摘要： A P channel MIS type semiconductor device have P type source and drain regions formed in a N type semiconductor substrate. Each source and drain regions are constructed the low and high impurity concentration layers. Channel side edges of the low concentration impurity layers arranged inside of the high concentration impurity layers. These double layer source and drain structure prevent the off set gate construction and the parasitic resistance.
摘要翻译： P沟道MIS型半导体器件具有形成在N型半导体衬底中的P型源区和漏区。每个源极和漏极区域被构造为低和高杂质浓度层。低浓度杂质层的通道侧边缘布置在高浓度杂质层的内部。这些双层源极和漏极结构防止了闭合栅极结构和寄生电阻。

5. 发明授权

US5747844A Dynamic semiconductor memory device with higher density bit line/word line layout 失效
公开(公告)号：US5747844A
公开(公告)日：1998-05-05
申请号：US736279
申请日：1996-10-24
申请人： Masami Aoki , Takashi Yamada , Hiroshi Takato , Tohru Ozaki , Katsuhiko Hieda , Akihiro Nitayama
发明人： Masami Aoki , Takashi Yamada , Hiroshi Takato , Tohru Ozaki , Katsuhiko Hieda , Akihiro Nitayama
IPC分类号： H01L21/822 , G11C11/401 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10817 , H01L27/0207 , H01L27/10852 , H01L27/10882 , Y10S257/907
摘要： A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.

6. 发明授权

US5578847A Dynamic semiconductor memory device with higher density bit line/word line layout 失效
标题翻译：具有更高密度位线/字线布局的动态半导体存储器件
公开(公告)号：US5578847A
公开(公告)日：1996-11-26
申请号：US402570
申请日：1995-03-13
申请人： Masami Aoki , Takashi Yamada , Hiroshi Takato , Tohru Ozaki , Katsuhiko Hieda , Akihiro Nitayama
发明人： Masami Aoki , Takashi Yamada , Hiroshi Takato , Tohru Ozaki , Katsuhiko Hieda , Akihiro Nitayama
IPC分类号： H01L21/822 , G11C11/401 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10817 , H01L27/0207 , H01L27/10852 , H01L27/10882 , Y10S257/907
摘要： A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.
摘要翻译：设置在一个位线BL上的多个位线触点布置在每个设置在每个相邻的两个字线WL之间的每隔一个空间中，并且设置在相邻位线BL上的多个位线触点彼此布置每个相邻的两个字线WL之间的空间不同于其中布置在前位线上形成的位线触点中的相应一个的空间。

7. 发明授权

US5258635A MOS-type semiconductor integrated circuit device 失效
标题翻译： MOS型半导体集成电路器件
公开(公告)号：US5258635A
公开(公告)日：1993-11-02
申请号：US754191
申请日：1991-08-28
申请人： Akihiro Nitayama , Hiroshi Takato , Fumio Horiguchi , Fujio Masuoka
发明人： Akihiro Nitayama , Hiroshi Takato , Fumio Horiguchi , Fujio Masuoka
IPC分类号： H01L27/092 , H01L27/11 , H01L29/78 , H01L29/26
CPC分类号： H01L27/0928 , H01L27/1104 , H01L29/7827 , Y10S257/904
摘要： A MOS-type semiconductor integrated circuit device is provided in which MOS transistors are formed in a vertical configuration. The MOS transistors are constituted by pillar layers formed on the substrate. The outer circumferential surfaces of the pillar layers are utilized to form the gates of the MOS transistors. Thus, large gate widths thereof can be obtained within a small area. As a result, the total chip area of the MOS transistors can be significantly reduced while maintaining a prescribed current-carrying capacity.
摘要翻译：提供了一种MOS型半导体集成电路器件，其中MOS晶体管形成为垂直配置。 MOS晶体管由形成在基板上的柱层构成。柱层的外周面用于形成MOS晶体管的栅极。因此，可以在小的区域内获得其大的栅极宽度。结果，可以在保持规定的载流能力的同时显着地减小MOS晶体管的总芯片面积。

8. 发明授权

US5923073A Method of manufacturing a semiconductor device and semiconductor device manufactured according to the method 失效
标题翻译：根据该方法制造的半导体器件和半导体器件的制造方法
公开(公告)号：US5923073A
公开(公告)日：1999-07-13
申请号：US932388
申请日：1997-09-17
申请人： Masami Aoki , Hiroshi Takato
发明人： Masami Aoki , Hiroshi Takato
IPC分类号： H01L21/20 , H01L21/302 , H01L21/3065 , H01L21/316 , H01L21/318 , H01L21/336 , H01L21/76 , H01L29/78 , H01L29/72
CPC分类号： H01L21/76 , Y10S148/015
摘要： A manufacturing method of semiconductor devices and semiconductor devices isolated by a trench portion. The trench portion is refilled with a Si epitaxial growth layer. The trench has a first insulating layer on its side wall and a second insulating layer formed by the oxidation in the self-alignment manner, as a cap layer, on the top portion of the trench. A semiconductor device formed on the substrate is isolated by the trench. The excessive leakage currents created by the stress between the substrate and the Si epitaxial layer are decreased. The concentration of the field effect at the corner portion of the trench is suppressed by the cap layer.The refilling step can be also made to a trench having the wider opening and another trench having the narrower opening simultaneously and uniformly.
摘要翻译：由沟槽部分隔离的半导体器件和半导体器件的制造方法。沟槽部分用Si外延生长层再填充。沟槽在其侧壁上具有第一绝缘层，并且在沟槽的顶部上以自对准方式氧化形成第二绝缘层作为覆盖层。形成在衬底上的半导体器件被沟槽隔离。由衬底和Si外延层之间的应力产生的过度的漏电流减小。通过盖层抑制沟槽角部处的场效应的集中。再填充步骤也可以同时且均匀地制成具有较宽开口的沟槽和具有较窄开口的另一个沟槽。

9. 发明授权

US06312982B1 Method of fabricating a trench capacitor 有权
标题翻译：制造沟槽电容器的方法
公开(公告)号：US06312982B1
公开(公告)日：2001-11-06
申请号：US09351182
申请日：1999-07-12
申请人： Hiroshi Takato , Koichi Kokubun
发明人： Hiroshi Takato , Koichi Kokubun
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L27/10829 , H01L27/10873 , H01L27/10894
摘要： This invention provides a semiconductor device by which a high-speed DRAM cell and logic circuit can be obtained without increasing the number of fabrication steps, and a method of fabricating the same. A memory cell is constructed of capacitors formed in two end portions of an element formation region of a silicon substrate and a MOS transistor formed between these capacitors. The interval between gate electrodes of MOS transistors in adjacent memory cells is made larger than the intervals between these gate electrodes and gate electrodes formed outside the former gate electrodes. A portion above an n-type diffusion layer connected to a capacitor node is filled with a spacer insulating film, and an n-type diffusion layer connected to a bit line is covered with the spacer insulating film. A titanium silicide film is formed on one of these n-type diffusion layers and the gate electrodes. In a first transistor in a memory cell array, a metal silicide film is not formed on the surfaces of source and drain diffusion layers and is formed only on the surface of a gate electrode. In a second transistor in a logic circuit, a metal silicide film is formed on the surfaces of source and drain diffusion layers and a gate electrode.
摘要翻译：本发明提供一种可以在不增加制造步骤的数量的情况下获得高速DRAM单元和逻辑电路的半导体器件及其制造方法。存储单元由形成在硅衬底的元件形成区域的两个端部中的电容器和形成在这些电容器之间的MOS晶体管构成。使相邻存储单元中的MOS晶体管的栅电极之间的间隔大于形成在前栅电极外的这些栅电极与栅电极之间的间隔。连接到电容器节点的n型扩散层上方的部分填充有间隔绝缘膜，并且与间位绝缘膜覆盖连接到位线的n型扩散层。在这些n型扩散层和栅电极之一上形成硅化钛膜。在存储单元阵列中的第一晶体管中，在源极和漏极扩散层的表面上不形成金属硅化物膜，并且仅形成在栅电极的表面上。在逻辑电路中的第二晶体管中，在源极和漏极扩散层和栅电极的表面上形成金属硅化物膜。

10. 发明授权

US6046487A Shallow trench isolation with oxide-nitride/oxynitride liner 失效
标题翻译：浅沟槽隔氧化氮化物/氮氧化物衬里
公开(公告)号：US6046487A
公开(公告)日：2000-04-04
申请号：US989303
申请日：1997-12-12
申请人： John Preston Benedict , David Mark Dobuzinsky , Philip Lee Flaitz , Erwin N. Hammerl , Herbert Ho , James F. Moseman , Herbert Palm , Seiko Yoshida , Hiroshi Takato
发明人： John Preston Benedict , David Mark Dobuzinsky , Philip Lee Flaitz , Erwin N. Hammerl , Herbert Ho , James F. Moseman , Herbert Palm , Seiko Yoshida , Hiroshi Takato
IPC分类号： H01L21/76 , H01L21/762 , H01L27/04
CPC分类号： H01L21/76232 , H01L21/762
摘要： Disclosed is an improved process and liner for trench isolation which includes either a single oxynitride layer or a dual oxynitride (or oxide)/nitride layer. Such a process and liner has an improved process window as well as being an effective O.sub.2 diffusion barrier and resistant to hot phosphoric and hydrofluoric acids.
摘要翻译：公开了用于沟槽隔离的改进的工艺和衬垫，其包括单一氮氧化物层或双氮氧化物（或氧化物）/氮化物层。这种工艺和衬里具有改进的工艺窗口，并且是有效的O 2扩散阻挡层并且耐热磷酸和氢氟酸。

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