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1. 发明授权

US06914453B2 Integrated logic and latch design with clock gating at static input signals 失效
标题翻译：具有静态输入信号时钟门控的集成逻辑和锁存器设计
公开(公告)号：US06914453B2
公开(公告)日：2005-07-05
申请号：US10616850
申请日：2003-07-10
申请人： Sang Hoo Dhong , Hwa-Joon Oh , Joel Abraham Silberman , Naoka Yano
发明人： Sang Hoo Dhong , Hwa-Joon Oh , Joel Abraham Silberman , Naoka Yano
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A method and an apparatus are provided for implementing a logic circuit with integrated logic and latch design. A clock input is provided to the logic circuit. One or more static signal inputs are further provided to the logic circuit. One or more dynamic signal inputs are generated by dynamically gating the one or more static signal inputs with the clock signal. The one or more dynamic signal inputs are applied to the logic circuit, and one or more dynamic signal outputs of the logic circuit are generated. The one or more dynamic signal outputs are precharged, and the one or more dynamic signal outputs are evaluated. The one or more dynamic signal outputs are held when the one or more dynamic signal outputs are neither being precharged nor being evaluated. The one or more dynamic signal outputs are converted into one or more static signal outputs.
摘要翻译：提供了一种用于实现具有集成逻辑和锁存器设计的逻辑电路的方法和装置。时钟输入提供给逻辑电路。一个或多个静态信号输入进一步提供给逻辑电路。通过用时钟信号动态选通一个或多个静态信号输入来产生一个或多个动态信号输入。一个或多个动态信号输入被施加到逻辑电路，并且产生逻辑电路的一个或多个动态信号输出。一个或多个动态信号输出被预充电，并且评估一个或多个动态信号输出。当一个或多个动态信号输出既不被预充电也不被评估时，一个或多个动态信号输出被保持。一个或多个动态信号输出被转换成一个或多个静态信号输出。

2. 发明授权

US5977808A Latch circuit and arithmetic unit having the same 失效
标题翻译：锁存电路和运算单元具有相同的功能
公开(公告)号：US5977808A
公开(公告)日：1999-11-02
申请号：US909949
申请日：1997-08-12
申请人： Naoka Yano , Hiroaki Murakami , Yukinori Muroya
发明人： Naoka Yano , Hiroaki Murakami , Yukinori Muroya
IPC分类号： H03K3/037 , H03K3/012 , H03K3/356
CPC分类号： H03K3/356121 , H03K3/012
摘要： A latch circuit receives complementary signals and consists of an nMOS transistor whose source is connected to an input terminal of the latch circuit and a series-connected circuit consisting of first and second pMOS transistors arranged between and connected to a drain terminal of the nMOS transistor and a high-potential power supply. The complementary signals are a first signal and a second signal that is an inversion of the first signal. Each of the signals has a pulse characteristic that rising time is longer than falling time. The latch circuit latches a quick fall by passing the first signal through the nMOS transistor. On the other hand, the latch circuit latches a slow rise by turning on the second pMOS transistor in response to a fall in the second signal.
摘要翻译：锁存电路接收互补信号并由其源极连接到锁存电路的输入端的nMOS晶体管和由位于nMOS晶体管的漏极端子之间并连接到nMOS晶体管的漏极端子的第一和第二pMOS晶体管组成的串联电路，高电位电源。互补信号是第一信号，第二信号是第一信号的反转。每个信号具有上升时间长于下降时间的脉冲特性。通过使第一信号通过nMOS晶体管，锁存电路锁存快速下降。另一方面，响应于第二信号的下降，锁存电路通过接通第二pMOS晶体管来锁存缓慢升高。

3. 发明授权

US06519621B1 Arithmetic circuit for accumulative operation 失效
标题翻译：累加运算的算术电路
公开(公告)号：US06519621B1
公开(公告)日：2003-02-11
申请号：US09307808
申请日：1999-05-10
申请人： Naoka Yano
发明人： Naoka Yano
IPC分类号： G06F700
CPC分类号： G06F7/5095 , G06F2207/3884
摘要： An improved arithmetic circuit for accumulative operation for use in digital signal processors, microprocessors and so forth is described, in which the pipelined control becomes effective during accumulative operation by eliminating idling stages in the pipeline structure. In accordance with the improved arithmetic circuit, during accumulative operation, the next operation is initiated with intermediate results of the current operation while the current operation is being executed and not yet completed so that it is possible to improve the speed of accumulative operation and reduce the scale of integration.
摘要翻译：描述了一种用于数字信号处理器，微处理器等中的累积运算的改进的运算电路，其中流水线控制在累积运行期间通过消除管线结构中的空转阶段而变得有效。根据改进的运算电路，在累加运算中，在当前运行正在执行中并没有完成的情况下，以当前运行的中间结果开始下一个运行，从而可以提高累加运行的速度并减少一体化规模

4. 发明授权

US06477557B1 Division circuit not requiring taking complements of divisor, dividend and remainder 有权
标题翻译：分割电路不需要对除数，股息和余数进行补充
公开(公告)号：US06477557B1
公开(公告)日：2002-11-05
申请号：US09521221
申请日：2000-03-08
申请人： Naoka Yano
发明人： Naoka Yano
IPC分类号： G06F752
CPC分类号： G06F7/535 , G06F2207/5352 , G06F2207/5353
摘要： In division process of restoring type or non-restoring type, a partial remainder is compared with a divisor in terms of absolute value. If the partial remainder is larger or both are equal, a quotient of its column is regarded as 1 and if small, the quotient of that column is regarded as 0 upon this division.
摘要翻译：在恢复类型或非恢复类型的划分过程中，将部分余数与绝对值的除数进行比较。如果部分余数较大或两者相等，则将其列的商视为1，如果小，则在该除法后将该列的商称为0。

5. 发明授权

US06286024B1 High-efficiency multiplier and multiplying method 失效
标题翻译：高效乘法和乘法法
公开(公告)号：US06286024B1
公开(公告)日：2001-09-04
申请号：US09156674
申请日：1998-09-18
申请人： Naoka Yano , Naoyuki Tamura
发明人： Naoka Yano , Naoyuki Tamura
IPC分类号： G06F752
CPC分类号： G06F7/5324
摘要： Upon execution of four sets of m/2 bit×n/2 bit multiplication, four multiplicand selectors select m/2-bit multiplicands respectively and four multiplicator selectors select corresponding n/2-bit multiplicators respectively, then the selected m/2-bit multiplicands and n/2-bit multiplicators are input into four multipliers, and then four sets of m/2 bit×n/2 bit multiplication are executed in parallel. Upon execution of m bit×n bit multiplication, the four multiplicand selectors select upper or lower m/2-bit multiplicands respectively and the four multiplicator selectors select upper or lower n/2-bit multiplicators respectively, then the selected m/2-bit multiplicands and n/2-bit multiplicators are input into the four multipliers respectively, then multiplication results of (lower m/2 bits of m bits)×(lower n/2 bits of n bits) and (upper m/2 bits of m bits)×(upper n/2 bits of n bits) out of four multiplication results of the four multipliers are connected by a connector, and then the connected multiplication results and the other two multiplication results are added by an adder with arranging in a predetermined bit location each other respectively.
摘要翻译：在执行四组m / 2位/ 2位乘法时，四个被乘数选择器分别选择m / 2位乘法器和四个乘法器选择器分别选择相应的n / 2位乘法器，然后选择的m / 2位乘法器和 n / 2位乘法器被输入到四个乘法器中，然后并行执行四组m / 2位x / 2位乘法。在执行m位位乘法时，四个被乘数选择器分别选择上位或下位m / 2位被乘数，并且四个乘法器选择器分别选择上位或下位n / 2位乘法器，然后选择的m / 2位被乘数和 n / 2位乘法器分别输入到四个乘法器中，然后（m位的较低m / 2位）x（n位的较低n / 2位）和（m位的上位m / 2位）通过连接器连接四个乘法器的四个相乘结果中的x（n位的上n / 2位），然后通过加法器将连接的乘法结果和其他两个乘法结果相加，并以预定位位置彼此分别。

6. 发明申请

US20050007152A1 Integrated logic and latch design with clock gating at static input signals 失效
公开(公告)号：US20050007152A1
公开(公告)日：2005-01-13
申请号：US10616850
申请日：2003-07-10
申请人： Sang Dhong , Hwa-Joon Oh , Joel Silberman , Naoka Yano
发明人： Sang Dhong , Hwa-Joon Oh , Joel Silberman , Naoka Yano
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A method and an apparatus are provided for implementing a logic circuit with integrated logic and latch design. A clock input is provided to the logic circuit. One or more static signal inputs are further provided to the logic circuit. One or more dynamic signal inputs are generated by dynamically gating the one or more static signal inputs with the clock signal. The one or more dynamic signal inputs are applied to the logic circuit, and one or more dynamic signal outputs of the logic circuit are generated. The one or more dynamic signal outputs are precharged, and the one or more dynamic signal outputs are evaluated. The one or more dynamic signal outputs are held when the one or more dynamic signal outputs are neither being precharged nor being evaluated. The one or more dynamic signal outputs are converted into one or more static signal outputs.

7. 发明授权

US6047305A Division circuit not requiring taking complements of divisor, dividend and remainder 失效
标题翻译：分割电路不需要对除数，股息和余数进行补充
公开(公告)号：US6047305A
公开(公告)日：2000-04-04
申请号：US55993
申请日：1998-04-07
申请人： Naoka Yano
发明人： Naoka Yano
IPC分类号： G06F7/38 , G06F7/52 , G06F7/535 , G06F7/537
CPC分类号： G06F7/535 , G06F2207/5352 , G06F2207/5353
摘要： In division process of restoring type or non-restoring type, a partial remainder is compared with a divisor in terms of absolute value. If the partial remainder is larger or both are equal, a quotient of its column is regarded as 1 and if smaller, the quotient of that column is regarded as 0 upon this division.
摘要翻译：在恢复类型或非恢复类型的划分过程中，将部分余数与绝对值的除数进行比较。如果部分余数较大或两者相等，则其列的商称为1，如果较小，则在该除法后将该列的商视为0。

8. 发明授权

US5675527A Multiplication device and sum of products calculation device 失效
标题翻译：乘法装置和产品计算装置总和
公开(公告)号：US5675527A
公开(公告)日：1997-10-07
申请号：US599966
申请日：1996-02-14
申请人： Naoka Yano
发明人： Naoka Yano
IPC分类号： G06F7/53 , G06F7/52 , G06F7/533 , G06F7/544 , G06F7/00
CPC分类号： G06F7/5324 , G06F7/5443 , G06F7/5338
摘要： In the first half of one cycle of a clock, a partial product generation circuit of each stage in a multiplication array generates partial products on the basis of one bit of the 16 low-order bits of multiplier data and the bits of multiplicand data. An accumulative addition circuit of each stage in the multiplication array accumulatively adds an initial value or an output from a previous accumulative addition circuit to the partial products to perform half necessary multiplication, writes the accumulative result in a latch as intermediate result data, and writes the predetermined number of bits of an output from the accumulative addition circuit of each stage at a predetermined bit position of the latch. In the second half of the clock, the partial product generation circuit of each stage generates partial products on the basis of one bit of an output from a latch holding the 16 high-order bits of a multiplier and the bits of the multiplicand data. In addition, the accumulative addition circuit of each stage accumulatively adds the intermediate result data or an output from a previous accumulative addition circuit to the partial products to perform the remaining half the calculation, and writes the final accumulative addition result and the predetermined number of bits of the output from the accumulative addition circuit of each stage in a latch.
摘要翻译：在时钟的一个周期的前半部分中，乘法阵列中的每个级的部分乘积生成电路基于乘法器数据的16个低位比特的一位和被乘数数据的比特来生成部分乘积。乘法阵列中的每个级的累积加法电路将来自先前累积加法电路的初始值或输出累加到部分乘积以执行一半必需乘法，将累加结果写入锁存器作为中间结果数据，并写入来自锁存器的预定位位置的每个级的累积加法电路的输出的预定数目的位。在后半部分，每个阶段的部分积产生电路基于来自保持乘法器的16个高阶位的锁存器的输出的一位和被乘数数据的比特来产生部分乘积。此外，各级的累积加法电路将中间结果数据或来自先前累积加法电路的输出累积到部分乘积中，以执行剩余的一半计算，并写入最终累加相加结果和预定位数在锁存器中每级的累积加法电路的输出。

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