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    • 10. 发明授权
    • Output buffer circuit and differential output buffer circuit, and transmission method
    • 输出缓冲电路和差分输出缓冲电路及其传输方式
    • US08324925B2
    • 2012-12-04
    • US13106926
    • 2011-05-13
    • Satoshi MuraokaNorio ChujoRitsuro Orihashi
    • Satoshi MuraokaNorio ChujoRitsuro Orihashi
    • H03K19/003
    • H03K19/018521
    • An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.
    • 输出缓冲器包括反相器,用于延迟输入信号的延迟电路,缓冲器和开关。 输出缓冲器将逻辑信号发送到传输路径,并且根据传输路径中的信号衰减量产生包括四种或更多种信号电压的波形。 缓冲器并联冗余连接,同时导通的缓冲器的数量由与缓冲器的输出电阻器串联提供的相应开关控制。 通过选择接通的开关的缓冲器,通过选择器逻辑选择信号调整预加重量和预加重抽头数,使预加重量变为可变,并使缓冲器的导通电阻保持恒定。