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1. 发明授权

US11087674B2 Subpixel circuitry for driving an associated light element, and method, display system and electronic device relating to same 有权
公开(公告)号：US11087674B2
公开(公告)日：2021-08-10
申请号：US16486026
申请日：2018-02-01
申请人： Nanyang Technological University , Massachusetts Institute of Technology , National University of Singapore
发明人： Joseph Sylvester Chang , Wei Shu , Yong Qu , Eugene A. Fitzgerald , Li Zhang , Eng Kian Kenneth Lee , Soo Jin Chua , Siau Ben Chiah
IPC分类号： G09G3/3225
摘要： Disclosed is a subpixel circuit 310 comprising: a first switching device 311 responsive to a digital periodic signal VP to provide a digital control signal VC relating to a digital data signal VD, the digital periodic signal VP defining 2N+1 time slots within each frame cycle, where N is a predetermined integer. The digital data signal VD has a predetermined value at a predetermined one of the 2N+1 time slots; and the subpixel circuit 310 further comprises a second switching device 312 responsive to the control signal Vc to drive an associated light emitting element 320.

2. 发明授权

US10847553B2 Method of forming a multilayer structure for a pixelated display and a multilayer structure for a pixelated display 有权
公开(公告)号：US10847553B2
公开(公告)日：2020-11-24
申请号：US16477095
申请日：2018-01-12
申请人： Massachusetts Institute of Technology , Nanyang Technological University , National University of Singapore
发明人： Li Zhang , Eng Kian Kenneth Lee , Soo Jin Chua , Eugene A. Fitzgerald , Siau Ben Chiah , Joseph Sylvester Chang , Yong Qu , Wei Shu , Kwang Hong Lee , Bing Wang
IPC分类号： H01L27/12 , H01L21/8238 , H01L25/00 , H01L33/00
CPC分类号： H01L27/1262 , H01L21/8238 , H01L25/50 , H01L27/124 , H01L33/005
摘要： A method of forming a multilayer structure for a pixelated display and a multilayer structure for a pixelated display is provided. The method comprising providing a first wafer comprising first layers disposed over a first substrate, said first layers comprising non-silicon based semiconductor material for forming p-n junction LEDs (light emitting devices); providing a second partially processed wafer comprising silicon-based CMOS (Complementary Metal Oxide Semiconductor) devices formed in second layers disposed over a second substrate, said CMOS devices for controlling the LEDs; and bonding the first and second wafers to form a composite wafer via a double-bonding transfer process.

3. 发明申请

US20190392755A1 Subpixel Circuit, And Display System And Electronic Device Having The Same 审中-公开
公开(公告)号：US20190392755A1
公开(公告)日：2019-12-26
申请号：US16486026
申请日：2018-02-01
申请人： Nanyang Technological University , Massachusetts Institute of Technology , National University of Singapore
发明人： Joseph Sylvester Chang , Wei Shu , Yong Qu , Eugene A. Fitzgerald , Li Zhang , Eng Kian Kenneth Lee , Soo Jin Chua , Siau Ben Chiah
IPC分类号： G09G3/3225
摘要： Disclosed is a subpixel circuit 310 comprising: a first switching device 311 responsive to a digital periodic signal VP to provide a digital control signal VC relating to a digital data signal VD, the digital periodic signal VP defining 2N+1 time slots within each frame cycle, where N is a predetermined integer. The digital data signal VD has a predetermined value at a predetermined one of the 2N+1 time slots; and the subpixel circuit 310 further comprises a second switching device 312 responsive to the control signal Vc to drive an associated light emitting element 320.

4. 发明授权

US10044326B2 Method of generating a pulse width modulation (PWM) signal for an analog amplifier, and a related pulse width modulator 有权
公开(公告)号：US10044326B2
公开(公告)日：2018-08-07
申请号：US14914768
申请日：2014-10-10
申请人： Nanyang Technological University
发明人： Joseph Sylvester Chang , Tong Ge , Linfei Guo
IPC分类号： H03F1/32 , H03F3/187 , H03F3/217 , H03F3/45 , G11C27/02 , H03F3/183 , H03K7/08
摘要： A method (300) of generating a pulse width modulation (PWM) signal for an analog amplifier, the amplifier arranged to receive an amplifier input signal having a magnitude, is disclosed. The method comprises receiving (302) a modulator input signal, which is associated with the amplifier input signal; and using (304) the modulator input signal to modulate a carrier to produce the PWM signal, wherein the carrier's frequency varies in dependence on the magnitude of the amplifier input signal. A related pulse width modulator is also disclosed.

5. 发明授权

US09866188B2 Dead time circuit for a switching circuit and a switching amplifier 有权
公开(公告)号：US09866188B2
公开(公告)日：2018-01-09
申请号：US15122577
申请日：2015-04-02
申请人： Nanyang Technological University
发明人： Joseph Sylvester Chang , Tong Ge , Linfei Guo
IPC分类号： H03F3/217 , H03K5/151 , H03K17/16 , H03K17/284
CPC分类号： H03F3/2171 , H03F3/217 , H03F3/2173 , H03F2200/351 , H03F2200/432 , H03K5/1515 , H03K17/162 , H03K17/284
摘要： A dead time circuit (750) for a switching circuit is disclosed. The dead-time circuit comprises: an input (752) for receiving a switching signal of the switching circuit with at least one supply rail having a ground bounce signal; first and second outputs (754a, 754b); a first feedforward path (756) coupled to the first output and arranged to receive the switching signal; a second feedforward path (758) coupled to the second output and arranged to receive the switching signal; a first feedback path (760) forming a first feedback loop between the first output and the second feedforward path; and a second feedback path (762) forming a second feedback loop between the second output and the first feedforward path; wherein each of the first and second feedforward paths includes a respective first and second delay circuit (764a, 764b), each having a time delay greater than a predetermined time period of the ground bounce signal. A switching amplifier is also disclosed.

6. 发明授权

US08994406B2 Digital cell 有权
标题翻译：数字电池
公开(公告)号：US08994406B2
公开(公告)日：2015-03-31
申请号：US13720867
申请日：2012-12-19
申请人： Nanyang Technological University
发明人： Joseph Sylvester Chang , Bah Hwee Gwee , Kwen Siong Chong
IPC分类号： H03K19/094 , H03K3/02 , H03K17/16 , H03K19/0185 , H03K19/20
CPC分类号： H03K17/165 , H03K19/0185 , H03K19/20
摘要： A digital cell for performing a logic operation on a logic input to produce a logic output, includes an evaluation block and a sense-amplifier block, both configured to receive input signals representative of the logic input, and to detect when the logic input and/or input signals validly encode at least one bit. The digital cell is configured to alternate between an evaluate state and a reset state. Upon the digital cell being in the reset state and the detection, the digital cell is switched from the reset state to the evaluate state in which the evaluation block generates a difference in its output signals, and the sense-amplifier block amplifies the difference so that the output signals encode at least one valid bit. Upon the digital cell being in the evaluate state, the digital cell can be triggered to reset to the reset state.
摘要翻译：用于在逻辑输入端执行逻辑运算以产生逻辑输出的数字单元包括评估块和读出放大器块，其被配置为接收代表逻辑输入的输入信号，并且检测逻辑输入和/ 或输入信号有效地编码至少一个位。数字单元被配置为在评估状态和复位状态之间交替。在数字单元处于复位状态和检测时，数字单元从复位状态切换到评估块产生其输出信号差异的评估状态，并且读出放大器块放大差值，使得输出信号编码至少一个有效位。当数字单元处于评估状态时，数字单元可以被触发以复位到复位状态。

7. 发明授权

US11218122B2 Supply modulator, power amplifier having the same, method for controlling the same, and method for controlling the power amplifier 有权
公开(公告)号：US11218122B2
公开(公告)日：2022-01-04
申请号：US16972909
申请日：2019-06-06
申请人： Nanyang Technological University
发明人： Joseph Sylvester Chang , Tong Ge , Huiqiao He , Linfei Guo
IPC分类号： H03G3/20 , H03F3/217 , H03F1/02 , H03F3/193
摘要： A supply modulator is provided, having a first amplifier circuit configured to generate a first electrical signal, a second amplifier circuit configured to generate a second electrical signal, the first and second electrical signals being for driving an electrical load, and a control circuit electrically coupled to the first and second amplifier circuits wherein the control circuit is configured to generate a pulsed electrical signal and to supply an output control signal to the second amplifier circuit for controlling generation of the second electrical output signal, wherein the supply modulator is configured to operate in two modes of operation, for the first amplifier circuit to generate the first electrical signals in response to quiescent current of the first amplifier circuit, for the control circuit to generate a modulated electrical signal in accordance with a clock signal in one mode, and, for the second amplifier circuit to operate.

8. 发明授权

US10913068B2 Testing device, microfluidic chip and nucleic acid testing method 有权
公开(公告)号：US10913068B2
公开(公告)日：2021-02-09
申请号：US15557957
申请日：2016-03-14
申请人： Nanyang Technological University , Agency for Science, Technology And Research , The Methodist Hospital
发明人： Joseph Sylvester Chang , Geok Soon Lim , Lei Zhang , Zhiping Wang , Ruige Wu , Stephen T. C. Wong , Kemi Cui
IPC分类号： B01L7/00 , C12Q1/686 , A61B5/15 , A61B5/153 , C12Q1/6851
摘要： A testing device is provided. The testing device includes a capturing tool and a microfluidic chip having a plurality of chambers connected in a network, a sample receiving port connected to the network, and a guide structure configured to receive the capturing tool, wherein the capturing tool is configured to capture sample in a distal position from the guide structure and further configured to transfer the captured sample to the sample receiving port in a proximal position from the guide structure.

9. 发明申请

US20130342253A1 DIGITAL CELL 有权
标题翻译：数字单元
公开(公告)号：US20130342253A1
公开(公告)日：2013-12-26
申请号：US13720867
申请日：2012-12-19
申请人： NANYANG TECHNOLOGICAL UNIVERSITY
发明人： Joseph Sylvester Chang , Bah Hwee Gwee , Kwen Siong Chong
IPC分类号： H03K17/16
CPC分类号： H03K17/165 , H03K19/0185 , H03K19/20
摘要： A digital cell for performing a logic operation on a logic input to produce a logic output, includes an evaluation block and a sense-amplifier block, both configured to receive input signals representative of the logic input, and to detect when the logic input and/or input signals validly encode at least one bit. The digital cell is configured to alternate between an evaluate state and a reset state. Upon the digital cell being in the reset state and the detection, the digital cell is switched from the reset state to the evaluate state in which the evaluation block generates a difference in its output signals, and the sense-amplifier block amplifies the difference so that the output signals encode at least one valid bit. Upon the digital cell being in the evaluate state, the digital cell can be triggered to reset to the reset state.
摘要翻译：用于在逻辑输入端执行逻辑运算以产生逻辑输出的数字单元包括评估块和读出放大器块，其被配置为接收代表逻辑输入的输入信号，并且检测逻辑输入和/ 或输入信号有效地编码至少一个位。数字单元被配置为在评估状态和复位状态之间交替。在数字单元处于复位状态和检测时，数字单元从复位状态切换到评估块产生其输出信号差异的评估状态，并且读出放大器块放大差值，使得输出信号编码至少一个有效位。当数字单元处于评估状态时，数字单元可以被触发以复位到复位状态。

10. 发明授权

US11356094B2 Circuit arrangements and methods for forming the same 有权
公开(公告)号：US11356094B2
公开(公告)日：2022-06-07
申请号：US16982408
申请日：2019-03-15
申请人： Nanyang Technological University
发明人： Joseph Sylvester Chang , Kwen Siong Chong , Ne Kyaw Zwa Lwin , Sivaramakrishnan Hariharakrishnan
IPC分类号： H03K19/003 , H01L27/02 , H03K17/082
摘要： A circuit arrangement is provided, having a first circuit configured to receive an input signal, and a second circuit configured to provide an output signal, wherein the first circuit includes a first pull-up network having a first transistor of a first conductivity type and a second transistor of a second conductivity type electrically coupled to each other, and a first pull-down network having a first transistor of the first conductivity type and a second transistor of the second conductivity type electrically coupled to each other, wherein the second circuit includes a second pull-up network having a first transistor of the first conductivity type, and a second pull-down network having a second transistor of the second conductivity type, wherein the first pull-up network and the second pull-down network are electrically coupled to each other, and wherein the first pull-down network and the second pull-up network are electrically coupled to each other.

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