专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050210546A1 Generation of plants with improved pathogen resistance 失效
标题翻译：产生具有改善的病原体抗性的植物
公开(公告)号：US20050210546A1
公开(公告)日：2005-09-22
申请号：US10512600
申请日：2003-04-24
申请人： Nancy Anne Federspiel , Allan Lammers , Xing Liang Liu , Stanley Bates , Christina Westerlund , Jonathan Fitch
发明人： Nancy Anne Federspiel , Allan Lammers , Xing Liang Liu , Stanley Bates , Christina Westerlund , Jonathan Fitch
IPC分类号： A01H1/00 , C07K14/415 , C12N5/04 , C12N15/29 , C12N15/82
CPC分类号： C12N15/8279 , C07K14/415 , C12N15/8281 , C12N15/8282
摘要： The present invention is directed to plants that display a pathogen resistance phenotype due to altered expression of a PPR2 nucleic acid. The invention is further directed to methods of generating plants with a pathogen resistance phenotype.
摘要翻译：本发明涉及由于PPR2核酸的表达改变而显示病原体抗性表型的植物。本发明进一步涉及产生具有病原体抗性表型的植物的方法。

2. 发明授权

US5668969A Address selective emulation routine pointer address mapping system 失效
标题翻译：地址选择性仿真例程指针地址映射系统
公开(公告)号：US5668969A
公开(公告)日：1997-09-16
申请号：US311880
申请日：1994-09-26
申请人： Jonathan Fitch
发明人： Jonathan Fitch
IPC分类号： G06F9/318 , G06F9/38 , G06F9/455 , G06F12/08 , G06F12/10
CPC分类号： G06F12/0802 , G06F9/45504
摘要： An address selective address mapping system comprises an address translation circuit, a central processing unit (CPU), a data cache, and a memory. The address outputs of the CPU are coupled to a first address bus, while the address inputs of the data cache and memory are coupled to a second address bus. The address translation circuit's inputs are coupled to the first address bus, and the address translation circuit's outputs are coupled to the second address bus. The CPU sends a pointer address via the first address bus to the address translation circuit. The address translation circuit determines whether the pointer address indicates that the next source instruction is within the subset of the most frequently executed source instructions. If so, the address translation circuit maps the pointer address to an address within the data cache. If not, the pointer address is routed through the address translation circuit unchanged. The pointer address is next routed to the data cache and to the RAM via the second address bus. If the pointer address was mapped to a data cache address, the data cache outputs the pointer to the next emulation routine on the data bus. If the pointer address was not mapped to a data cache address, the pointer to the next emulation routine is output to the data bus at the data outputs of the memory. The present invention also includes a method for manufacturing an address selective address mapping system.
摘要翻译：地址选择性地址映射系统包括地址转换电路，中央处理单元（CPU），数据高速缓存和存储器。 CPU的地址输出耦合到第一地址总线，而数据高速缓存和存储器的地址输入耦合到第二地址总线。地址转换电路的输入耦合到第一地址总线，并且地址转换电路的输出耦合到第二地址总线。 CPU经由第一地址总线发送指针地址到地址转换电路。地址转换电路确定指针地址是否指示下一个源指令位于最常执行的源指令的子集内。如果是，则地址转换电路将指针地址映射到数据高速缓存内的地址。如果不是，指针地址通过地址转换电路不变地被路由。指针地址接下来通过第二个地址总线路由到数据高速缓存和RAM。如果指针地址映射到数据高速缓存地址，则数据高速缓存将指针指向数据总线上的下一个仿真程序。如果指针地址未映射到数据高速缓存地址，则在存储器的数据输出端将指向下一个仿真程序的指针输出到数据总线。本发明还包括一种地址选择性地址映射系统的制造方法。

3. 发明授权

US5056060A Printed circuit card with self-configuring memory system for non-contentious allocation of reserved memory space among expansion cards 失效
标题翻译：具有自配置存储器系统的印刷电路卡，用于在扩展卡之间非争用分配保留的存储空间
公开(公告)号：US5056060A
公开(公告)日：1991-10-08
申请号：US464952
申请日：1990-01-16
申请人： Jonathan Fitch , Ronald Hochsprung
发明人： Jonathan Fitch , Ronald Hochsprung
IPC分类号： G06F12/06 , G06F13/42
CPC分类号： G06F13/4217 , G06F12/0661
摘要： A printed circuit board card adapted to fit into a slot and make electrical connections with cooperating terminals in the slot, the slot being disposed on the main circuit board of a personal computer system, the main circuit board including a CPU, memory, a 32-bit address bus with control signals associated therewith, and input/output circuity. The slot is coupled to the 32-bit address bus, being substantially a NUBUS bus, and the slot includes distinct identification line means which provide the slot with an identification number (distinct number) in the computer system. The card includes a decoder means which is coupled to the slot to receive the identification number; the decoder means has memory reservation means which causes 256 megabytes of memory space to be reserved for the card in the slot, such that, where the slot number is X, the 256 megabytes of reserved memory space begins at location $X000 0000 and ends at location $XFFF FFFF.
摘要翻译：一种印刷电路板卡，其适于装配到狭槽中，并与所述槽中的配合端子进行电连接，所述槽设置在个人计算机系统的主电路板上，所述主电路板包括CPU，存储器，具有与其相关联的控制信号的位地址总线以及输入/输出电路。该时隙耦合到32位地址总线，其基本上是NUBUS总线，并且该时隙包括不同的标识线装置，其在计算机系统中为该时隙提供标识号（不同号码）。该卡片包括一个解码器装置，该解码装置耦合到该插槽以接收该识别号码; 解码器装置具有存储器预留装置，其使得为时隙中的卡预留256兆字节的存储器空间，使得在时隙号为X的情况下，256兆字节的保留存储空间从位置$ X000 0000开始并以位置$ XFFF FFFF。

4. 发明申请

US20110232556A1 SAIL HANDLING MECHANISM THAT SECURES A HEADBOARD TO A HEADCAR 有权
标题翻译：将头架安装在头盔上的SAIL操作机构
公开(公告)号：US20110232556A1
公开(公告)日：2011-09-29
申请号：US12730092
申请日：2010-03-23
申请人： Jonathan Fitch
发明人： Jonathan Fitch
IPC分类号： B63H9/06 , B63H9/08
CPC分类号： B63H9/08
摘要： A mechanism to raise and lower the sail of a boat includes a headcar movably secured to a mast of the boat and a headboard affixed to the sail. A pulling force applied to a halyard raises the sail and causes the headboard to engage the headcar. When the sail is lowered, the headboard disengages from the headcar so that the sail furls flat on the boom.
摘要翻译：用于升高和降低船的帆的机构包括可移动地固定到船的桅杆的头车头和固定到帆的床头板。施加到一个仓库的拉力引起帆，并使床头板接合头车。当帆下降时，床头板与头车脱离，使得风帆在吊杆上平展。

5. 发明授权

US5574887A Apparatus and method for emulation routine pointer prefetch 失效
标题翻译：用于仿真例程指针预取的装置和方法
公开(公告)号：US5574887A
公开(公告)日：1996-11-12
申请号：US124315
申请日：1993-09-20
申请人： Jonathan Fitch
发明人： Jonathan Fitch
IPC分类号： G06F9/318 , G06F3/00 , H01J9/00
CPC分类号： G06F9/3017
摘要： An apparatus and method for emulation routine pointer prefetch are disclosed. The apparatus includes an emulated program counter (EPC), a prefetch state machine, a summing device, an opcode storage device, and a pointer storage device. The EPC, opcode storage device and pointer storage device are coupled to a bus to receive, store and output an emulated program counter value, an opcode value and a pointer to a next emulation routine. The EPC, opcode storage device, and pointer storage device are controlled by the prefetch state machine, which also is coupled to the bus to detect a reference to a reserved memory address and stores an updated emulated program counter value in the EPC using the summing device. The prefetch state machine uses the EPC value to prefetch the next source instruction to be emulated in a first memory operation. A portion of the prefetched source instruction is the opcode value and is stored in the opcode storage device. The prefetch state machine uses the opcode value in a second memory operation to retrieve a pointer to a corresponding emulation routine which is stored in the pointer storage device. The method for emulation routine pointer prefetch preferably comprises the steps of determining if a currently executing emulation routine has issued an instruction to update the EPC; prefetching a next source instruction based upon the value of the EPC; and using an opcode within the prefetched source instruction to prefetch a pointer to a next emulation routine corresponding to the prefetched source instruction.
摘要翻译：公开了一种用于仿真例程指针预取的装置和方法。该装置包括仿真程序计数器（EPC），预取状态机，求和装置，操作码存储装置和指针存储装置。 EPC，操作码存储设备和指针存储设备耦合到总线以接收，存储和输出仿真程序计数器值，操作码值和指向下一个仿真程序的指针。 EPC，操作码存储设备和指针存储设备由预取状态机控制，预取状态机也耦合到总线以检测对保留的存储器地址的引用，并使用求和设备将更新的仿真程序计数器值存储在EPC中。预取状态机使用EPC值在第一个存储器操作中预取要被仿真的下一个源指令。预取源指令的一部分是操作码值，并存储在操作码存储装置中。预取状态机在第二存储器操作中使用操作码值来检索指向存储在指针存储装置中的对应仿真程序的指针。用于仿真例程指针预取的方法优选地包括以下步骤：确定当前执行的仿真程序是否已经发出更新EPC的指令; 根据EPC的值预取下一个源指令; 以及在预取源指令内使用操作码来预取指向与预取源指令相对应的下一个仿真程序的指针。

6. 发明授权

US5392408A Address selective emulation routine pointer address mapping system 失效
标题翻译：地址选择性仿真例程指针地址映射系统
公开(公告)号：US5392408A
公开(公告)日：1995-02-21
申请号：US124302
申请日：1993-09-20
申请人： Jonathan Fitch
发明人： Jonathan Fitch
IPC分类号： G06F9/318 , G06F9/38 , G06F9/455 , G06F12/08 , G06F12/10
CPC分类号： G06F12/0802 , G06F9/45504
摘要： An instruction mapping system comprises an instruction mapping circuit, a central processing unit (CPU), a data cache, and a memory. The address outputs of the CPU are coupled to a first address bus, while the address inputs of the data cache and memory are coupled to a second address bus. The instruction mapping circuit's address inputs are coupled to the first address bus, and the instruction mapping circuit's outputs are coupled to the second address bus. The CPU sends a pointer address via the first address bus to the instruction mapping circuit. The instruction mapping circuit determines whether the pointer address indicates that the next source instruction is within the subset of most frequently executed source instructions. If so, the instruction mapping circuit maps the pointer address to an address within the data cache. If not, the pointer address is routed through the instruction mapping circuit unchanged. The pointer address is next routed to the data cache and to the RAM via the second address bus. If the pointer address was mapped to a data cache address, the data cache outputs the pointer to the next emulation routine on the data bus. If the pointer address was not mapped to a data cache address, the pointer to the next emulation routine is output on the data bus at the data outputs of the memory. The present invention also includes a method for manufacturing an instruction mapping system.
摘要翻译：指令映射系统包括指令映射电路，中央处理单元（CPU），数据高速缓存和存储器。 CPU的地址输出耦合到第一地址总线，而数据高速缓存和存储器的地址输入耦合到第二地址总线。指令映射电路的地址输入耦合到第一地址总线，并且指令映射电路的输出耦合到第二地址总线。 CPU通过第一地址总线将指针地址发送到指令映射电路。指令映射电路确定指针地址是否指示下一个源指令在最常执行的源指令的子集内。如果是这样，指令映射电路将指针地址映射到数据高速缓存内的地址。如果不是，指针地址通过指令映射电路不变地被路由。指针地址接下来通过第二个地址总线路由到数据高速缓存和RAM。如果指针地址映射到数据高速缓存地址，则数据高速缓存将指针指向数据总线上的下一个仿真程序。如果指针地址未映射到数据高速缓存地址，则在存储器的数据输出处，在数据总线上输出指向下一个仿真程序的指针。本发明还包括用于制造指令映射系统的方法。

7. 发明授权

US08161898B2 Sail handling mechanism that secures a headboard to a headcar 有权
标题翻译：将头饰固定在头饰上的风帆处理机构
公开(公告)号：US08161898B2
公开(公告)日：2012-04-24
申请号：US12730092
申请日：2010-03-23
申请人： Jonathan Fitch
发明人： Jonathan Fitch
IPC分类号： B63H9/04
CPC分类号： B63H9/08
摘要： A mechanism to raise and lower the sail of a boat includes a headcar movably secured to a mast of the boat and a headboard affixed to the sail. A pulling force applied to a halyard raises the sail and causes the headboard to engage the headcar. When the sail is lowered, the headboard disengages from the headcar so that the sail furls flat on the boom.
摘要翻译：用于升高和降低船的帆的机构包括可移动地固定到船的桅杆的头车头和固定到帆的床头板。施加到一个仓库的拉力引起帆，并使床头板接合头车。当帆下降时，床头板与头车脱离，使得风帆在吊杆上平展。

8. 发明授权

US5408622A Apparatus and method for emulation routine control transfer via host jump instruction creation and insertion 失效
标题翻译：通过主机跳转指令创建和插入进行仿真程序控制传输的装置和方法
公开(公告)号：US5408622A
公开(公告)日：1995-04-18
申请号：US125940
申请日：1993-09-23
申请人： Jonathan Fitch
发明人： Jonathan Fitch
IPC分类号： G06F9/318 , G06F12/00
CPC分类号： G06F9/3017
摘要： An apparatus for emulation routine control transfer creates a jump host instruction (JHI) containing the address of a next emulation routine during the execution of a current emulation routine and outputs the JHI at the end of current emulation routine for transfer of host processor control. The apparatus preferably comprises: an emulated program counter (EPC), a summing means, a state machine, a pointer storage means, an opcode storage means, and a jump instruction circuit. The state machine is preferably coupled to control the loading of the EPC, the loading of the opcode storage means, the summing means, the pointer storage means and the operation of the jump instruction circuit. The pointer storage means is preferably coupled between the data bus and the jump instruction circuit. The state machine preferably issues commands on the control bus and directly to the summing means and the jump instruction circuit to prefetch the next emulation routine, create a jump instruction to the beginning of the next emulation routine and assert the jump instruction on the bus at the appropriate time to transfer directly from one emulation routine to the next using the single host jump instruction. The jump host instruction is placed upon the host processor's instruction bus after execution of the final instruction within a current emulation routine. Thus, the execution of the next emulation routine begins immediately after the execution of the jump host instruction, and significant amounts of processing time associated with the dispatch loop are eliminated.
摘要翻译：用于仿真例程控制传送的装置在执行当前仿真程序期间产生包含下一个仿真程序的地址的跳转主机指令（JHI），并在当前仿真程序结束时输出JHI以传送主处理器控制。该装置优选地包括：仿真程序计数器（EPC），求和装置，状态机，指针存储装置，操作码存储装置和跳转指令电路。状态机优选地被耦合以控制EPC的加载，操作码存储装置的加载，求和装置，指针存储装置和跳转指令电路的操作。指针存储装置优选地耦合在数据总线和跳转指令电路之间。状态机优选地在控制总线上发出命令，并且直接向求和装置和跳转指令电路预取下一个仿真程序，创建到下一个仿真程序开始的跳转指令，并在该总线上断言跳转指令使用单个主机跳转指令的适当时间直接从一个仿真程序传输到下一个仿真程序。在当前仿真程序中执行最终指令之后，跳转主机指令被置于主机处理器的指令总线上。因此，下一个仿真程序的执行在执行跳转主机指令之后立即开始，并且消除与调度循环相关联的大量处理时间。

9. 发明授权

US5361389A Apparatus and method for emulation routine instruction issue 失效
标题翻译：仿真程序指令问题的装置和方法
公开(公告)号：US5361389A
公开(公告)日：1994-11-01
申请号：US127254
申请日：1993-09-27
申请人： Jonathan Fitch
发明人： Jonathan Fitch
IPC分类号： G06F9/318 , G06F9/38 , G06F9/455
CPC分类号： G06F9/3017
摘要： An apparatus for emulation routine instruction issue comprises a bus signal router, a state machine, a virtual program counter (VPC) circuit, an emulated program counter (EPC), a summing circuit, an opcode storage register, and a pointer storage register. The VPC circuit maintains the VPC value under the direction of the state machine. In response to a next instruction request issued by the central processing unit (CPU), the state machine outputs the VPC to an instruction address bus, transferring the host instruction stored at the address indicated by the VPC to the instruction bus for issue to the CPU. After a next host instruction request, the state machine updates the VPC value. Concurrent with the execution of the current emulation routine, the state machine prefetches the nest emulation routine pointer (NERP) by issuing DMA commands and commands to the EPC, the opcode storage means, and the pointer storage means. If the final host instruction in the current emulation routine has been reached, the state machine assigns the NERP to the VPC and outputs the VPC to the instruction address bus. A method for Emulation Routine Instruction Issue comprises the steps of determining if a next host instruction request has been made by the CPU; outputting the VPC to the instruction address bus; and updating the VPC; and prefetching the NERP concurrent with the execution of the host instructions in the current emulation routine.
摘要翻译：用于仿真例程指令的装置包括总线信号路由器，状态机，虚拟程序计数器（VPC）电路，仿真程序计数器（EPC），求和电路，操作码存储寄存器和指针存储寄存器。 VPC电路在状态机的方向下维持VPC值。响应于由中央处理单元（CPU）发出的下一个指令请求，状态机将VPC输出到指令地址总线，将存储在由VPC指示的地址存储的主机指令传送到指令总线以发送给CPU 。在下一个主机指令请求之后，状态机更新VPC值。与执行当前仿真例程一起，状态机通过向EPC，操作码存储装置和指针存储装置发出DMA命令和命令来预取嵌套仿真例程指针（NERP）。如果当前仿真程序中的最终主机指令已经到达，则状态机将NERP分配给VPC，并将VPC输出到指令地址总线。一种用于仿真程序指令的方法包括以下步骤：确定CPU是否已经做出下一个主机指令请求; 将VPC输出到指令地址总线; 并更新VPC; 并且在当前仿真程序中与主机指令的执行同时预取NERP。

10. 发明授权

US4931923A Computer system for automatically reconfigurating memory space to avoid overlaps of memory reserved for expansion slots 失效
标题翻译：用于自动重新配置存储空间的计算机系统，以避免为扩展槽预留的内存重叠
公开(公告)号：US4931923A
公开(公告)日：1990-06-05
申请号：US25499
申请日：1987-03-13
申请人： Jonathan Fitch , Ronald Hochsprung
发明人： Jonathan Fitch , Ronald Hochsprung
IPC分类号： G06F12/06 , G06F13/42
CPC分类号： G06F13/4217 , G06F12/0661
摘要： A personal computer system includes a main circuit board having a central processing unit and expansion slots each of which is adapted to receive a printed circuit board card. The main circuit board further includes memory, a 32-bit address bus with control signals associated therewith, and input/output circuitry. The slot is coupled to the 32-bit address bus, which is substantially a NUBUS bus, and the slot includes distinct identification line means which provide the slot with an identification number (distinct number) in the computer system. The computer system reserves 256-megabytes of memory space ranging from location $X000 0000 to location $XFFF FFFF for memory on a card in a slot having a distinct number equal to $X.
摘要翻译：个人计算机系统包括具有中央处理单元和扩展槽的主电路板，每个扩展槽适于接收印刷电路板卡。主电路板还包括存储器，具有与其相关联的控制信号的32位地址总线和输入/输出电路。该时隙耦合到基本上是NUBUS总线的32位地址总线，并且该时隙包括在计算机系统中为该时隙提供标识号（不同号码）的不同的标识线装置。计算机系统保留256MB的存储空间，从位置$ X000 0000到位置$ XFFF FFFF，用于存储器在具有不同数量等于$ X的插槽中的存储器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式