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1. 发明授权

US08614571B2 Apparatus and method for on-chip sampling of dynamic IR voltage drop 有权
标题翻译：用于片上采样动态IR电压降的装置和方法
公开(公告)号：US08614571B2
公开(公告)日：2013-12-24
申请号：US13299445
申请日：2011-11-18
申请人： Nan-Hsin Tseng , Chin-Chou Liu , Saurabh Gupta , Ji-Jan Chen , Chi Wei Hu
发明人： Nan-Hsin Tseng , Chin-Chou Liu , Saurabh Gupta , Ji-Jan Chen , Chi Wei Hu
IPC分类号： G01R19/00 , G01R27/08
CPC分类号： G01R19/16552 , G01R19/2503 , G01R31/31924
摘要： Test points on an integrated circuit chip, especially points subject to IR voltage drop along power supply rails, are coupled to comparators controlled by an automatic test controller, all included on the chip. Each test point can have one or more comparators and one or more reference voltages over a testing range. A change of state at a comparator sets a latch that is read and reset by the on-chip automatic test controller during test intervals. The automatic test controller can coordinate with external automatic test equipment that applies stimulus signals to the chip during testing. The greatest voltage drop during a test interval is determined from the latched output of the switched comparator coupled to the lowest reference voltage. The setting and resetting of the latch can be gated through a selectable delay so as to discriminate for excursions that persist for a longer or shorter time.
摘要翻译：集成电路芯片上的测试点，特别是沿着电源轨的IR电压降的点被耦合到由芯片上所有的自动测试控制器控制的比较器。每个测试点可以在测试范围内具有一个或多个比较器和一个或多个参考电压。比较器状态的改变设置在测试间隔期间由片上自动测试控制器读取和复位的锁存器。自动测试控制器可以在测试期间与外部自动测试设备进行协调，并将激励信号施加到芯片。测试间隔期间的最大电压降由耦合到最低参考电压的开关比较器的锁存输出确定。闩锁的设置和复位可以通过可选择的延迟来选通，以便区分持续更长或更短时间的偏移。

2. 发明授权

US08832511B2 Built-in self-test for interposer 有权
标题翻译：内置自检功能
公开(公告)号：US08832511B2
公开(公告)日：2014-09-09
申请号：US13209477
申请日：2011-08-15
申请人： Ji-Jan Chen , Nan-Hsin Tseng , Chin-Chou Liu
发明人： Ji-Jan Chen , Nan-Hsin Tseng , Chin-Chou Liu
IPC分类号： G01R31/28
CPC分类号： G01R31/318536
摘要： A device includes a first die coupled to an interconnect structure of an interposer. The first die includes a first BIST circuit configured to generate and output test signals to the interconnection structure of the interposer. A second die is coupled to the interconnect structure of the interposer and includes a second BIST circuit configured to receive signals from the interconnection structure of the interposer in response to the first BIST circuit transmitting the test signals. The second BIST circuit is configured to compare the signals received from the interconnection structure of the interposer to reference signals generated by the second BIST circuit.
摘要翻译：器件包括耦合到插入器的互连结构的第一管芯。第一裸片包括第一BIST电路，其被配置为产生并输出测试信号到中介层的互连结构。第二管芯耦合到插入器的互连结构，并且包括第二BIST电路，其被配置为响应于第一BIST电路发送测试信号而从插入器的互连结构接收信号。第二BIST电路被配置为将从插入器的互连结构接收的信号与由第二BIST电路产生的参考信号进行比较。

3. 发明申请

US20130047049A1 BUILT-IN SELF-TEST FOR INTERPOSER 有权
标题翻译：内置自检测试
公开(公告)号：US20130047049A1
公开(公告)日：2013-02-21
申请号：US13209477
申请日：2011-08-15
申请人： Ji-Jan CHEN , Nan-Hsin Tseng , Chin-Chou Liu
发明人： Ji-Jan CHEN , Nan-Hsin Tseng , Chin-Chou Liu
IPC分类号： G01R31/3187 , G06F11/27
CPC分类号： G01R31/318536
摘要： A device includes a first die coupled to an interconnect structure of an interposer. The first die includes a first BIST circuit configured to generate and output test signals to the interconnection structure of the interposer. A second die is coupled to the interconnect structure of the interposer and includes a second BIST circuit configured to receive signals from the interconnection structure of the interposer in response to the first BIST circuit transmitting the test signals. The second BIST circuit is configured to compare the signals received from the interconnection structure of the interposer to reference signals generated by the second BIST circuit.
摘要翻译：器件包括耦合到插入器的互连结构的第一管芯。第一裸片包括第一BIST电路，其被配置为产生并输出测试信号到中介层的互连结构。第二管芯耦合到插入器的互连结构，并且包括第二BIST电路，其被配置为响应于第一BIST电路发送测试信号而从插入器的互连结构接收信号。第二BIST电路被配置为将从插入器的互连结构接收的信号与由第二BIST电路产生的参考信号进行比较。

4. 发明授权

US08113412B1 Methods for detecting defect connections between metal bumps 有权
标题翻译：检测金属凸块之间缺陷连接的方法
公开(公告)号：US08113412B1
公开(公告)日：2012-02-14
申请号：US13107476
申请日：2011-05-13
申请人： Nan-Hsin Tseng , Yun-Han Lee , Chin-Chou Liu , Ji-Jan Chen , Wei-Pin Changchien , Chien-Hui Chen
发明人： Nan-Hsin Tseng , Yun-Han Lee , Chin-Chou Liu , Ji-Jan Chen , Wei-Pin Changchien , Chien-Hui Chen
IPC分类号： B23K31/02 , B23K31/12
CPC分类号： G01R31/2853 , G01R31/307
摘要： A method includes electrically grounding a first plurality of metal bumps on a first surface of an interconnection component to a common ground plate. A voltage contrast (VC) image of a second plurality of metal bumps of the interconnection component is generated. Grey levels of the second plurality of metal bumps in the VC image are analyzed to find defect connections between the second plurality of metal bumps and respective ones of the first plurality of metal bumps.
摘要翻译：一种方法包括将互连部件的第一表面上的第一多个金属凸块电接地到公共接地板。产生互连部件的第二多个金属凸块的电压对比度（VC）图像。分析VC图像中的第二多个金属凸块的灰度级，以发现第二多个金属凸块和第一多个金属凸块中的相应的金属凸块之间的缺陷连接。

5. 发明授权

US07986591B2 Ultra high resolution timing measurement 有权
标题翻译：超高分辨率时序测量
公开(公告)号：US07986591B2
公开(公告)日：2011-07-26
申请号：US12757396
申请日：2010-04-09
申请人： Nan-Hsin Tseng , Chin-Chou Liu , Saurabh Gupta
发明人： Nan-Hsin Tseng , Chin-Chou Liu , Saurabh Gupta
IPC分类号： G04F8/00 , G01R13/02
CPC分类号： G04F10/005
摘要： An integrated circuit for high-resolution timing measurement includes a delay pulse generator, the first oscillator to generate the first clock with the first frequency, the second oscillator to generate the second clock with the second frequency, an oscillator tuner, a sampling module, a counter, wherein the delay pulse generator generated a delayed pulse from the second clock, the oscillator tuner controls the second frequency to be as close as possible to the first frequency without being the same as the second frequency, the sampling module samples the delayed pulse at the first frequency, the counter generates a digital counter value by counting a number of sampling by the sampling module, and a time width of the delayed pulse can be calculated by the digital counter value. The second oscillator can be a tunable ring oscillator with one or more coarse tune stages and one or more fine-tune stages.
摘要翻译：用于高分辨率定时测量的集成电路包括延迟脉冲发生器，第一振荡器，用于产生具有第一频率的第一时钟，第二振荡器产生具有第二频率的第二时钟，振荡器调谐器，采样模块，计数器，其中所述延迟脉冲发生器从所述第二时钟产生延迟脉冲，所述振荡器调谐器控制所述第二频率尽可能接近所述第一频率而不与所述第二频率相同，所述采样模块将所述延迟脉冲采样第一频率，计数器通过对采样模块进行采样次数的计数来产生数字计数器值，并且可以通过数字计数器值计算延迟脉冲的时间宽度。第二振荡器可以是具有一个或多个粗调级和一个或多个微调级的可调谐环形振荡器。

6. 发明授权

US08305847B2 Ultra high resolution timing measurement 有权
标题翻译：超高分辨率时序测量
公开(公告)号：US08305847B2
公开(公告)日：2012-11-06
申请号：US13110735
申请日：2011-05-18
申请人： Nan-Hsin Tseng , Chin-Chou Liu , Saurabh Gupta
发明人： Nan-Hsin Tseng , Chin-Chou Liu , Saurabh Gupta
IPC分类号： G04F8/00 , G01R13/02
CPC分类号： G04F10/005
摘要： A method for high-resolution timing measurement includes a first oscillator generating a first clock with a first frequency. A second oscillator generates a second clock with a second frequency. A delay pulse generator generates a delayed pulse from the second clock. An oscillator tuner controls the second frequency to be as close as possible to the first frequency without being the same as the first frequency. A sampling module samples the delayed pulse at the first frequency. A counter generates a digital counter value by counting a number of samples made by the sampling module.
摘要翻译：用于高分辨率定时测量的方法包括产生具有第一频率的第一时钟的第一振荡器。第二振荡器产生具有第二频率的第二时钟。延迟脉冲发生器从第二时钟产生延迟的脉冲。振荡器调谐器控制第二频率尽可能接近于第一频率，而不与第一频率相同。采样模块以第一个频率采样延迟脉冲。计数器通过对由采样模块进行的采样数进行计数来产生数字计数器值。

7. 发明授权

US08339155B2 System and method for detecting soft-fails 有权
标题翻译：检测软故障的系统和方法
公开(公告)号：US08339155B2
公开(公告)日：2012-12-25
申请号：US12857270
申请日：2010-08-16
申请人： Nan-Hsin Tseng , Chin-Chou Liu , Wei-Pin Changchien , Kin Lam Tong
发明人： Nan-Hsin Tseng , Chin-Chou Liu , Wei-Pin Changchien , Kin Lam Tong
IPC分类号： H03K19/00 , H03K19/23
CPC分类号： H03K19/23 , G01R31/31816
摘要： A system and method for detecting soft-failures in integrated circuits is provided. A circuit includes a combinatorial logic block having a first signal input and a second signal input, and a latch coupled to an output of the combinatorial logic block. The combinatorial logic block produces a pulse when only one of either a first signal provided by the first signal input or a second signal provided by the second signal input is a logical high value, and the latch captures the pulse if the pulse has a pulse width greater than a second threshold. The pulse has a pulse width that is based on a timing difference between a first signal transition on the first signal and a second signal transition on the second signal, the combinatorial logic block produces the pulse if the timing difference is greater than a first threshold, and the combinatorial logic block operates with balanced inputs.
摘要翻译：提供一种用于检测集成电路中的软故障的系统和方法。电路包括具有第一信号输入和第二信号输入的组合逻辑块，以及耦合到组合逻辑块的输出的锁存器。当仅由第一信号输入提供的第一信号或由第二信号输入提供的第二信号中的一个信号是逻辑高值时，组合逻辑块产生脉冲，并且如果脉冲具有脉冲宽度，则锁存器捕捉脉冲大于第二阈值。脉冲具有基于第一信号上的第一信号转换与第二信号上的第二信号转换之间的定时差的脉冲宽度，如果定时差大于第一阈值，组合逻辑块产生脉冲，并且组合逻辑块通过平衡输入进行操作。

8. 发明申请

US20120038388A1 RC Delay Detectors with High Sensitivity for Through Substrate Vias 有权
标题翻译：具有高灵敏度的RC延迟检测器用于穿透基板通孔
公开(公告)号：US20120038388A1
公开(公告)日：2012-02-16
申请号：US12971204
申请日：2010-12-17
申请人： Nan-Hsin Tseng , Chin-Chou Liu , Wei-Pin Changchien , Pei-Ying Lin , Ta-Wen Hung
发明人： Nan-Hsin Tseng , Chin-Chou Liu , Wei-Pin Changchien , Pei-Ying Lin , Ta-Wen Hung
IPC分类号： H03K19/21 , H03K17/00
CPC分类号： H03K19/23 , G01R31/31816 , H03K19/17764
摘要： A die includes a plurality of through-substrate vias (TSVs) penetrating a substrate of the die, wherein the plurality of TSVs are grouped as a plurality of TSV pairs. A plurality of contact pads is coupled to the plurality of TSVs, wherein the plurality of contact pads is exposed on a first surface of the die. The die further includes a plurality of balanced pulse comparison units, wherein each of the plurality of balanced pulse comparison units includes a first input and a second input coupled to a first TSV and a second TSV of one of the plurality of TSV pairs. The die further includes a plurality of pulse latches, each including an input coupled to an output of one of the plurality of balanced pulse comparison units.
摘要翻译：芯片包括贯穿芯片的衬底的多个贯穿衬底通孔（TSV），其中多个TSV被分组为多个TSV对。多个接触焊盘耦合到多个TSV，其中多个接触焊盘暴露在模具的第一表面上。芯片还包括多个平衡脉冲比较单元，其中多个平衡脉冲比较单元中的每一个包括耦合到多个TSV对之一的第一TSV和第二TSV的第一输入和第二输入。芯片还包括多个脉冲锁存器，每个脉冲锁存器包括耦合到多个平衡脉冲比较单元之一的输出的输入端。

9. 发明授权

US08384430B2 RC delay detectors with high sensitivity for through substrate vias 有权
标题翻译： RC延迟检测器，通过基板通孔具有高灵敏度
公开(公告)号：US08384430B2
公开(公告)日：2013-02-26
申请号：US12971204
申请日：2010-12-17
申请人： Nan-Hsin Tseng , Chin-Chou Liu , Wei-Pin Changchien , Pei-Ying Lin , Ta-Wen Hung
发明人： Nan-Hsin Tseng , Chin-Chou Liu , Wei-Pin Changchien , Pei-Ying Lin , Ta-Wen Hung
IPC分类号： H03K19/21 , H03K17/00
CPC分类号： H03K19/23 , G01R31/31816 , H03K19/17764
摘要： A die includes a plurality of through-substrate vias (TSVs) penetrating a substrate of the die, wherein the plurality of TSVs are grouped as a plurality of TSV pairs. A plurality of contact pads is coupled to the plurality of TSVs, wherein the plurality of contact pads is exposed on a first surface of the die. The die further includes a plurality of balanced pulse comparison units, wherein each of the plurality of balanced pulse comparison units includes a first input and a second input coupled to a first TSV and a second TSV of one of the plurality of TSV pairs. The die further includes a plurality of pulse latches, each including an input coupled to an output of one of the plurality of balanced pulse comparison units.
摘要翻译：芯片包括贯穿芯片的衬底的多个贯穿衬底通孔（TSV），其中多个TSV被分组为多个TSV对。多个接触焊盘耦合到多个TSV，其中多个接触焊盘暴露在管芯的第一表面上。芯片还包括多个平衡脉冲比较单元，其中多个平衡脉冲比较单元中的每一个包括耦合到多个TSV对之一的第一TSV和第二TSV的第一输入和第二输入。芯片还包括多个脉冲锁存器，每个脉冲锁存器包括耦合到多个平衡脉冲比较单元之一的输出的输入端。

10. 发明申请

US20110121856A1 System and Method for Detecting Soft-Fails 有权
标题翻译：检测软件的系统和方法
公开(公告)号：US20110121856A1
公开(公告)日：2011-05-26
申请号：US12857270
申请日：2010-08-16
申请人： Nan-Hsin Tseng , Chin-Chou Liu , Wei-Pin Changchien , Kin Lam Tong
发明人： Nan-Hsin Tseng , Chin-Chou Liu , Wei-Pin Changchien , Kin Lam Tong
IPC分类号： H03K19/00 , H03K19/23
CPC分类号： H03K19/23 , G01R31/31816
摘要： A system and method for detecting soft-failures in integrated circuits is provided. A circuit includes a combinatorial logic block having a first signal input and a second signal input, and a latch coupled to an output of the combinatorial logic block. The combinatorial logic block produces a pulse when only one of either a first signal provided by the first signal input or a second signal provided by the second signal input is a logical high value, and the latch captures the pulse if the pulse has a pulse width greater than a second threshold. The pulse has a pulse width that is based on a timing difference between a first signal transition on the first signal and a second signal transition on the second signal, the combinatorial logic block produces the pulse if the timing difference is greater than a first threshold, and the combinatorial logic block operates with balanced inputs.
摘要翻译：提供一种用于检测集成电路中的软故障的系统和方法。电路包括具有第一信号输入和第二信号输入的组合逻辑块，以及耦合到组合逻辑块的输出的锁存器。当仅由第一信号输入提供的第一信号或由第二信号输入提供的第二信号中的一个信号是逻辑高值时，组合逻辑块产生脉冲，并且如果脉冲具有脉冲宽度，则锁存器捕捉脉冲大于第二阈值。脉冲具有基于第一信号上的第一信号转换与第二信号上的第二信号转换之间的定时差的脉冲宽度，如果定时差大于第一阈值，组合逻辑块产生脉冲，并且组合逻辑块通过平衡输入进行操作。

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