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1. 发明申请

US20140189300A1 Processing Core Having Shared Front End Unit 审中-公开
标题翻译：具有共享前端单元的处理核心
公开(公告)号：US20140189300A1
公开(公告)日：2014-07-03
申请号：US13730719
申请日：2012-12-28
申请人： Name ILAN PARDO , DROR MARKOVICH , OREN BEN-KIKI , YUVAL YOSEF
发明人： Name ILAN PARDO , DROR MARKOVICH , OREN BEN-KIKI , YUVAL YOSEF
IPC分类号： G06F15/76
CPC分类号： G06F9/3891 , G06F9/30123 , G06F9/3802 , G06F9/3818 , G06F9/3851
摘要： A processor having one or more processing cores is described. Each of the one or more processing cores has front end logic circuitry and a plurality of processing units. The front end logic circuitry is to fetch respective instructions of threads and decode the instructions into respective micro-code and input operand and resultant addresses of the instructions. Each of the plurality of processing units is to be assigned at least one of the threads, is coupled to said front end unit, and has a respective buffer to receive and store microcode of its assigned at least one of the threads. Each of the plurality of processing units also comprises: i) at least one set of functional units corresponding to a complete instruction set offered by the processor, the at least one set of functional units to execute its respective processing unit's received microcode; ii) registers coupled to the at least one set of functional units to store operands and resultants of the received microcode; iii) data fetch circuitry to fetch input operands for the at least one functional units' execution of the received microcode.
摘要翻译：描述具有一个或多个处理核的处理器。一个或多个处理核心中的每一个具有前端逻辑电路和多个处理单元。前端逻辑电路是提取线程的相应指令，并将指令解码为相应的微码和指令的输入操作数和结果地址。多个处理单元中的每一个将被分配至少一个线程，耦合到所述前端单元，并且具有相应的缓冲器以接收和存储其分配的至少一个线程的微代码。所述多个处理单元中的每一个还包括：i）至少一组对应于由所述处理器提供的完整指令集的功能单元，所述至少一组功能单元执行其各自处理单元的接收到的微代码; ii）耦合到所述至少一组功能单元的寄存器，以存储所接收的微代码的操作数和结果; iii）数据获取电路，用于获取至少一个功能单元执行所接收的微代码的输入操作数。

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