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1. 发明申请

US20070055823A1 Multi-interface, controller, memory card having the multi-interface controller, and interface setting method 有权
标题翻译：具有多接口控制器的多接口，控制器，存储卡，以及接口设置方法
公开(公告)号：US20070055823A1
公开(公告)日：2007-03-08
申请号：US11496150
申请日：2006-07-31
申请人： Nam-Phil Jo , Min-Soo Kang , Chang-Il Son
发明人： Nam-Phil Jo , Min-Soo Kang , Chang-Il Son
IPC分类号： G06F12/00 , H05K7/10
CPC分类号： G06F13/387 , G06F3/0601 , G06F2003/0692
摘要： A multi-interface controller having a first logic circuit and a second logic circuit. The first logic circuit supports a first interface. The second logic circuit supports a second interface. The first logic circuit is enabled based on a first command. The second logic circuit is enabled based on a second command.
摘要翻译：一种具有第一逻辑电路和第二逻辑电路的多接口控制器。第一逻辑电路支持第一接口。第二逻辑电路支持第二接口。基于第一命令启用第一逻辑电路。基于第二命令启用第二逻辑电路。

2. 发明授权

US07987308B2 Multi-interface controller, memory card having the multi-interface controller, and interface setting method 有权
标题翻译：多接口控制器，具有多接口控制器的存储卡，以及接口设置方法
公开(公告)号：US07987308B2
公开(公告)日：2011-07-26
申请号：US11496150
申请日：2006-07-31
申请人： Nam-Phil Jo , Min-Soo Kang , Chang-IL Son
发明人： Nam-Phil Jo , Min-Soo Kang , Chang-IL Son
IPC分类号： H05K7/10 , G06F9/44
CPC分类号： G06F13/387 , G06F3/0601 , G06F2003/0692
摘要： A multi-interface controller having a first logic circuit and a second logic circuit. The first logic circuit supports a first interface. The second logic circuit supports a second interface. The first logic circuit is enabled based on a first command. The second logic circuit is enabled based on a second command.
摘要翻译：一种多接口控制器，具有第一逻辑电路和第二逻辑电路。第一逻辑电路支持第一接口。第二逻辑电路支持第二接口。基于第一命令启用第一逻辑电路。基于第二命令启用第二逻辑电路。

3. 发明申请

US20080034142A1 Data transfer in memory card system 有权
标题翻译：存储卡系统中的数据传输
公开(公告)号：US20080034142A1
公开(公告)日：2008-02-07
申请号：US11881601
申请日：2007-07-27
申请人： Nam-Phil Jo , Chang-Il Son , Kyu-Hyun Shim , Sin-Ho Yang
发明人： Nam-Phil Jo , Chang-Il Son , Kyu-Hyun Shim , Sin-Ho Yang
IPC分类号： G06F13/38
CPC分类号： G06F12/0246 , G06F1/12 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G06F13/385 , G06F13/423 , G06F2003/0697
摘要： A memory card system includes a host that issues a read command and a memory card that upon receiving the read command sends read data to the host in synchronism with a read clock signal generated within the memory card. In addition, the memory card sends the read clock signal to the host, and the host receives the read data in synchronism with the read clock signal, for increasing the allowable setup time period at the host.
摘要翻译：存储卡系统包括发出读取命令的主机和存储卡，在接收到读取命令时，与存储卡内生成的读取时钟信号同步地向主机发送读取数据。此外，存储卡将读取的时钟信号发送到主机，并且主机与读取的时钟信号同步地接收读取的数据，以增加主机的允许的建立时间段。

4. 发明授权

US08423703B2 Data transfer in memory card system 有权
公开(公告)号：US08423703B2
公开(公告)日：2013-04-16
申请号：US11881601
申请日：2007-07-27
申请人： Nam-Phil Jo , Chang-Il Son , Kyu-Hyun Shim , Sin-Ho Yang
发明人： Nam-Phil Jo , Chang-Il Son , Kyu-Hyun Shim , Sin-Ho Yang
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F3/00
CPC分类号： G06F12/0246 , G06F1/12 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G06F13/385 , G06F13/423 , G06F2003/0697
摘要： A memory card system includes a host that issues a read command and a memory card that upon receiving the read command sends read data to the host in synchronism with a read clock signal generated within the memory card. In addition, the memory card sends the read clock signal to the host, and the host receives the read data in synchronism with the read clock signal, for increasing the allowable setup time period at the host.

5. 发明授权

US07660170B2 Methods of operating non-volatile memory devices to generate data strobe signals during data reading and related devices 有权
标题翻译：在数据读取和相关设备期间操作非易失性存储器件以产生数据选通信号的方法
公开(公告)号：US07660170B2
公开(公告)日：2010-02-09
申请号：US11565351
申请日：2006-11-30
申请人： Nam-Phil Jo
发明人： Nam-Phil Jo
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C16/26
摘要： A non-volatile memory device includes a latch unit, a non-volatile memory cell array configured to store data, and a control unit. The control unit is configured to receive a read command and a read address output from a memory controller, generate a data strobe signal based on the received read command, read data corresponding to the received read address from the non-volatile memory cell array, and output the read data to the latch unit. The latch unit is configured to output the data output from the control unit to the memory controller in response to the data strobe signal. Related methods of operation are also discussed.
摘要翻译：非易失性存储器件包括锁存单元，被配置为存储数据的非易失性存储单元阵列和控制单元。控制单元被配置为接收从存储器控制器输出的读取命令和读取地址，基于接收到的读取命令，从非易失性存储单元阵列生成对应于接收到的读取地址的读取数据的数据选通信号，以及将读取的数据输出到锁存单元。闩锁单元被配置为响应于数据选通信号将从控制单元输出的数据输出到存储器控制器。还讨论了相关的操作方法。

6. 发明授权

US08301986B2 Memory system and method for providing error correction 有权
标题翻译：用于提供纠错的存储系统和方法
公开(公告)号：US08301986B2
公开(公告)日：2012-10-30
申请号：US12390700
申请日：2009-02-23
申请人： Nam-Phil Jo , Dae-Han Youn
发明人： Nam-Phil Jo , Dae-Han Youn
IPC分类号： H03M13/00
CPC分类号： H03M13/1545 , G06F11/1068 , H03M13/151 , H03M13/1575 , H03M13/3715
摘要： An error correction decoder includes a syndrome computation circuit, an error correction and computation circuit and an error correction circuit. The syndrome computation circuit calculates a syndrome of read data. The error correction and computation circuit calculates a location of a single-bit error using a division operation between elements of the syndrome when the single-bit error exists in the read data. The error correction circuit corrects the single-bit error of the read data based on the location of the single-bit error.
摘要翻译：纠错解码器包括校正子计算电路，纠错和计算电路以及纠错电路。校正子计算电路计算读数据的校正子。误差校正和计算电路在读数据中存在单位错误时，使用校正子元素之间的除法运算来计算单位误差的位置。误差校正电路根据单位错误的位置校正读取数据的单位错误。

7. 发明申请

US20080140869A1 Circuits and Methods for Correcting Errors in Downloading Firmware 审中-公开
标题翻译：修正下载固件错误的电路和方法
公开(公告)号：US20080140869A1
公开(公告)日：2008-06-12
申请号：US11737281
申请日：2007-04-19
申请人： Nam-Phil Jo
发明人： Nam-Phil Jo
IPC分类号： G06F3/00
CPC分类号： G06F11/10
摘要： An electronic device operating using firmware can include a nonvolatile memory and an interface circuit that is configured to receive a firmware data signal transmission from external to the electronic device, where the firmware data signal includes error correction codes. An error correction circuit is coupled to the interface circuit and to the nonvolatile memory, and is configured to repair errors introduced into the firmware data signal during transmission of the firmware data signal to provide a corrected firmware data signal at the electronic device and to store the corrected firmware data signal in the nonvolatile memory.
摘要翻译：使用固件操作的电子设备可以包括非易失性存储器和接口电路，其被配置为从外部向电子设备接收固件数据信号传输，其中固件数据信号包括纠错码。错误校正电路耦合到接口电路和非易失性存储器，并且被配置为在固件数据信号的传输期间修复引入到固件数据信号中的错误，以便在电子设备处提供校正的固件数据信号并存储在非易失性存储器中校正固件数据信号。

8. 发明申请

US20080101138A1 METHODS OF OPERATING NON-VOLATILE MEMORY DEVICES TO GENERATE DATA STROBE SIGNALS DURING DATA READING AND RELATED DEVICES 有权
标题翻译：在数据读取期间操作非易失性存储器件以产生数据结构信号的方法和相关设备
公开(公告)号：US20080101138A1
公开(公告)日：2008-05-01
申请号：US11565351
申请日：2006-11-30
申请人： Nam-Phil Jo
发明人： Nam-Phil Jo
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C16/26
摘要： A non-volatile memory device includes a latch unit, a non-volatile memory cell array configured to store data, and a control unit. The control unit is configured to receive a read command and a read address output from a memory controller, generate a data strobe signal based on the received read command, read data corresponding to the received read address from the non-volatile memory cell array, and output the read data to the latch unit. The latch unit is configured to output the data output from the control unit to the memory controller in response to the data strobe signal. Related methods of operation are also discussed.
摘要翻译：非易失性存储器件包括锁存单元，被配置为存储数据的非易失性存储单元阵列和控制单元。控制单元被配置为接收从存储器控制器输出的读取命令和读取地址，基于接收到的读取命令，从非易失性存储单元阵列生成对应于接收到的读取地址的读取数据的数据选通信号，以及将读取的数据输出到锁存单元。闩锁单元被配置为响应于数据选通信号将从控制单元输出的数据输出到存储器控制器。还讨论了相关的操作方法。

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