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1. 发明申请

US20110042746A1 SINGLE TRANSISTOR MEMORY DEVICE HAVING SOURCE AND DRAIN INSULATING REGIONS AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：具有源极和漏极绝缘区域的单晶体管存储器件及其制造方法
公开(公告)号：US20110042746A1
公开(公告)日：2011-02-24
申请号：US12940304
申请日：2010-11-05
申请人： Nam-Kyun Tak , Ki-Whan Song , Chang-Woo Oh , Woo-Yeong Cho
发明人： Nam-Kyun Tak , Ki-Whan Song , Chang-Woo Oh , Woo-Yeong Cho
IPC分类号： H01L29/772
CPC分类号： H01L27/108 , H01L27/10802 , H01L29/0653 , H01L29/1045 , H01L29/7834 , H01L29/7841
摘要： A single transistor floating-body dynamic random access memory (DRAM) device includes a floating body located on a semiconductor substrate and a gate electrode located on the floating body, the floating body including an excess carrier storage region. The DRAM device further includes source and drain regions respectively located at both sides of the gate electrode, and leakage shielding patterns located between the floating body and the source and drain regions. Each of the source and drain regions contact the floating body, which may be positioned between the source and drain regions. The floating body may also laterally extend under the leakage shielding patterns, which may be arranged at outer sides of the gate electrode.
摘要翻译：单晶体管浮体动态随机存取存储器（DRAM）器件包括位于半导体衬底上的浮体和位于浮体上的栅电极，浮体包括过剩的载流子存储区。 DRAM器件还包括分别位于栅极两侧的源极和漏极区域以及位于浮体与源极和漏极区域之间的泄漏屏蔽图案。源极和漏极区域中的每一个接触可以位于源极和漏极区域之间的浮体。浮体还可以横向延伸在泄漏屏蔽图案下方，这可以布置在栅电极的外侧。

2. 发明授权

US07851859B2 Single transistor memory device having source and drain insulating regions and method of fabricating the same 有权
标题翻译：具有源极和漏极绝缘区域的单晶体管存储器件及其制造方法
公开(公告)号：US07851859B2
公开(公告)日：2010-12-14
申请号：US11829113
申请日：2007-07-27
申请人： Nam-Kyun Tak , Ki-Whan Song , Chang-Woo Oh , Woo-Yeong Cho
发明人： Nam-Kyun Tak , Ki-Whan Song , Chang-Woo Oh , Woo-Yeong Cho
IPC分类号： H01L23/62
CPC分类号： H01L27/108 , H01L27/10802 , H01L29/0653 , H01L29/1045 , H01L29/7834 , H01L29/7841
摘要： A single transistor floating-body dynamic random access memory (DRAM) device includes a floating body located on a semiconductor substrate and a gate electrode located on the floating body, the floating body including an excess carrier storage region. The DRAM device further includes source and drain regions respectively located at both sides of the gate electrode, and leakage shielding patterns located between the floating body and the source and drain regions. Each of the source and drain regions contact the floating body, which may be positioned between the source and drain regions. The floating body may also laterally extend under the leakage shielding patterns, which may be arranged at outer sides of the gate electrode.
摘要翻译：单晶体管浮体动态随机存取存储器（DRAM）器件包括位于半导体衬底上的浮体和位于浮体上的栅电极，浮体包括过剩的载流子存储区。 DRAM器件还包括分别位于栅极两侧的源极和漏极区域以及位于浮体与源极和漏极区域之间的泄漏屏蔽图案。源极和漏极区域中的每一个接触可以位于源极和漏极区域之间的浮体。浮体还可以横向延伸在泄漏屏蔽图案下方，这可以布置在栅电极的外侧。

3. 发明授权

US07969808B2 Memory cell structures, memory arrays, memory devices, memory controllers, and memory systems, and methods of manufacturing and operating the same 失效
标题翻译：存储单元结构，存储器阵列，存储器件，存储器控制器和存储器系统，以及制造和操作存储器单元结构的方法
公开(公告)号：US07969808B2
公开(公告)日：2011-06-28
申请号：US12171406
申请日：2008-07-11
申请人： Ki-Whan Song , Nam-Kyun Tak
发明人： Ki-Whan Song , Nam-Kyun Tak
IPC分类号： G11C11/00
CPC分类号： H01L27/108 , G11C11/406 , G11C11/40618 , G11C11/40622 , G11C2211/4016 , H01L27/10802 , H01L29/7841
摘要： Example embodiments are directed to memory cell structures, memory arrays, memory devices, memory controllers, and memory systems using bipolar junction transistor (BJT) operation.
摘要翻译：示例性实施例涉及使用双极结型晶体管（BJT）操作的存储器单元结构，存储器阵列，存储器件，存储器控制器和存储器系统。

4. 发明申请

US20070146008A1 Semiconductor circuit comprising vertical transistor 审中-公开
标题翻译：半导体电路包括垂直晶体管
公开(公告)号：US20070146008A1
公开(公告)日：2007-06-28
申请号：US11581390
申请日：2006-10-17
申请人： Nam-Kyun Tak , Ki-Whan Song
发明人： Nam-Kyun Tak , Ki-Whan Song
IPC分类号： H03K19/094
CPC分类号： H03F3/45183 , H01L27/0207 , H01L27/10897 , H01L29/66666 , H03F3/195 , H03F3/45188 , H03F2203/45292 , H03F2203/45352
摘要： A semiconductor circuit comprising a vertical transistor is disclosed. A differential amplifier circuit comprises a pair of amplification transistors, wherein the pair of amplification transistors comprises a first amplification transistor adapted to receive, amplify, and output a differential input signal. The first amplification transistor is a first vertical transistor comprising a first top and a first bottom, and the first top is a first drain of the first vertical transistor and the first bottom is a first source of the first vertical transistor. The differential amplifier circuit further comprises a current source electrically disposed between the pair of amplification transistors and a second power supply to form a current path between a first power supply and the second power supply.
摘要翻译：公开了一种包括垂直晶体管的半导体电路。差分放大器电路包括一对放大晶体管，其中该对放大晶体管包括适于接收，放大和输出差分输入信号的第一放大晶体管。第一放大晶体管是包括第一顶部和第一底部的第一垂直晶体管，第一顶部是第一垂直晶体管的第一漏极，第一底部是第一垂直晶体管的第一源极。差分放大器电路还包括电气设置在一对放大晶体管之间的电流源和第二电源，以在第一电源和第二电源之间形成电流路径。

5. 发明授权

US08054693B2 Capacitorless dynamic memory device capable of performing data read/restoration and method for operating the same 失效
标题翻译：能够执行数据读取/恢复的电容式动态存储器件及其操作方法
公开(公告)号：US08054693B2
公开(公告)日：2011-11-08
申请号：US12654283
申请日：2009-12-16
申请人： Ki-Whan Song , Nam-Kyun Tak
发明人： Ki-Whan Song , Nam-Kyun Tak
IPC分类号： G11C16/04
CPC分类号： G11C11/404 , G11C11/4076 , G11C2211/4016
摘要： In example embodiments, the semiconductor memory device, and the method for operating the semiconductor memory device, includes a memory cell array having a plurality of memory cells each formed of a transistor having a floating body. The transistors are coupled between a plurality of word lines, a plurality of source lines and a plurality of bit lines. Additionally, the memory cell array includes a controller configured to read data from at least one of the memory cells and restore data to the memory cell storing a first data state through a bit operation of the memory cell. The controller restores data to the memory cell by applying a first source-line control voltage to a selected source line and applying a first word-line control voltage to a selected word line in a first period of a read operation. Also, the controller is configured to restore data to the memory cell, which is storing a second data state, by applying a second source-line control voltage to the selected source line and applying a second word-line control voltage to the selected word line in a second period of the read operation.
摘要翻译：在示例实施例中，半导体存储器件以及用于操作半导体存储器件的方法包括具有多个存储单元的存储单元阵列，每个存储单元均由具有浮体的晶体管形成。晶体管耦合在多个字线，多条源极线和多个位线之间。此外，存储单元阵列包括控制器，其被配置为从存储器单元中的至少一个读取数据，并且通过存储器单元的位操作将数据恢复到存储第一数据状态的存储单元。控制器通过对所选择的源极线施加第一源极线控制电压并且在读取操作的第一周期中对所选择的字线施加第一字线控制电压来将数据恢复到存储器单元。此外，控制器被配置为通过对所选择的源极线施加第二源极线控制电压并将第二字线控制电压施加到所选择的字线来将数据恢复到存储第二数据状态的存储器单元在读操作的第二周期。

6. 发明申请

US20090278194A1 Capacitorless one-transistor semiconductor memory device having improved data retention abilities and operation characteristics 有权
标题翻译：具有改进的数据保存能力和操作特性的无电容的一晶体管半导体存储器件
公开(公告)号：US20090278194A1
公开(公告)日：2009-11-12
申请号：US12453036
申请日：2009-04-28
申请人： Nam-Kyun Tak , Ki-Whan Song
发明人： Nam-Kyun Tak , Ki-Whan Song
IPC分类号： H01L29/792 , H01L29/786
CPC分类号： H01L29/7841 , H01L29/785
摘要： A capacitorless one transistor (1T) semiconductor device whose data storage abilities are increased and leakage current is reduced is provided. The capacitor-less 1T semiconductor device includes a buried insulating layer formed on a substrate, an active region formed on the buried insulating layer and including a source region, a drain region and a floating body formed between the source region and the drain region, and a gate pattern formed on the floating body, wherein the floating body includes a main floating body having the same top surface height as one of the source region and the drain region, and a first upper floating body formed between the main floating body and the gate pattern.
摘要翻译：提供其数据存储能力增加并且漏电流减小的无电容器一晶体管（1T）半导体器件。电容器1T半导体器件包括形成在基板上的掩埋绝缘层，形成在掩埋绝缘层上的有源区，并且包括源区域，漏极区域和形成在源极区域与漏极区域之间的浮体，以及形成在所述浮体上的栅极图案，其中所述浮体包括具有与所述源极区域和所述漏极区域中的一个相同的顶部高度的主浮动体，以及形成在所述主浮体和所述栅极之间的第一上浮体模式。

7. 发明申请

US20090022003A1 MEMORY CELL STRUCTURES, MEMORY ARRAYS, MEMORY DEVICES, MEMORY CONTROLLERS, AND MEMORY SYSTEMS, AND METHODS OF MANUFACTURING AND OPERATING THE SAME 失效
标题翻译：存储器单元结构，存储器阵列，存储器件，存储器控制器和存储器系统及其制造和操作方法
公开(公告)号：US20090022003A1
公开(公告)日：2009-01-22
申请号：US12171406
申请日：2008-07-11
申请人： Ki-Whan SONG , Nam-Kyun Tak
发明人： Ki-Whan SONG , Nam-Kyun Tak
IPC分类号： G11C7/00 , H01L27/108
CPC分类号： H01L27/108 , G11C11/406 , G11C11/40618 , G11C11/40622 , G11C2211/4016 , H01L27/10802 , H01L29/7841
摘要： Example embodiments are directed to memory cell structures, memory arrays, memory devices, memory controllers, and memory systems using bipolar junction transistor (BJT) operation.
摘要翻译：示例性实施例涉及使用双极结型晶体管（BJT）操作的存储器单元结构，存储器阵列，存储器件，存储器控制器和存储器系统。

8. 发明授权

US08179736B2 Antifuses and program circuits having the same 有权
标题翻译：防潮和程序电路具有相同的功能
公开(公告)号：US08179736B2
公开(公告)日：2012-05-15
申请号：US12654282
申请日：2009-12-16
申请人： Nam-Kyun Tak , Ki-Whan Song
发明人： Nam-Kyun Tak , Ki-Whan Song
IPC分类号： G11C17/18
CPC分类号： H01L23/5252 , G11C17/18 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： Antifuses and program circuits having the same. The antifuses are embodied as a transistor. When a first power supply voltage is applied to a source, a first program voltage for causing impact ionization is applied to a gate and drain, and a second program voltage for causing channel initiated secondary electron/channel initiated secondary hole (CHISEL/CHISHL) is applied to a well, a dielectric material may be ruptured between the gate adjacent to the drain and the well so that an antifuse may be programmed.
摘要翻译：防潮和程序电路具有相同的功能。反熔丝体现为晶体管。当向源极施加第一电源电压时，将用于引起冲击电离的第一编程电压施加到栅极和漏极，并且用于引起通道引发的次级电子/通道引发的次级孔（CHISEL / CHISHL）的第二编程电压为应用于阱，电介质材料可能在与漏极和阱之间相邻的栅极之间破裂，从而可以对反熔丝进行编程。

9. 发明申请

US20110221001A1 Memory cell structures, memory arrays, memory devices, memory controllers, and memory systems, and methods of manufacturing and operating the same 审中-公开
公开(公告)号：US20110221001A1
公开(公告)日：2011-09-15
申请号：US13067239
申请日：2011-05-18
申请人： Ki-Whan Song , Nam-Kyun Tak
发明人： Ki-Whan Song , Nam-Kyun Tak
IPC分类号： H01L29/78
CPC分类号： H01L27/108 , G11C11/406 , G11C11/40618 , G11C11/40622 , G11C2211/4016 , H01L27/10802 , H01L29/7841
摘要： Example embodiments are directed to memory cell structures, memory arrays, memory devices, memory controllers, and memory systems using bipolar junction transistor (BJT) operation.

10. 发明申请

US20100149898A1 Antifuses and program circuits having the same 有权
标题翻译：防潮和程序电路具有相同的功能
公开(公告)号：US20100149898A1
公开(公告)日：2010-06-17
申请号：US12654282
申请日：2009-12-16
申请人： Nam-Kyun Tak , Ki-Whan Song
发明人： Nam-Kyun Tak , Ki-Whan Song
IPC分类号： G11C17/16 , H01L29/78 , G11C5/14
CPC分类号： H01L23/5252 , G11C17/18 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： Antifuses and program circuits having the same. The antifuses are embodied as a transistor. When a first power supply voltage is applied to a source, a first program voltage for causing impact ionization is applied to a gate and drain, and a second program voltage for causing channel initiated secondary electron/channel initiated secondary hole (CHISEL/CHISHL) is applied to a well, a dielectric material may be ruptured between the gate adjacent to the drain and the well so that an antifuse may be programmed.
摘要翻译：防潮和程序电路具有相同的功能。反熔丝体现为晶体管。当向源极施加第一电源电压时，将用于引起冲击电离的第一编程电压施加到栅极和漏极，并且用于引起通道引发的次级电子/通道引发的次级孔（CHISEL / CHISHL）的第二编程电压为应用于阱，电介质材料可能在与漏极和阱之间相邻的栅极之间破裂，从而可以对反熔丝进行编程。

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