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1. 发明授权

US09690582B2 Instruction and logic for cache-based speculative vectorization 有权
公开(公告)号：US09690582B2
公开(公告)日：2017-06-27
申请号：US14143576
申请日：2013-12-30
申请人： Nalini Vasudevan , Youfeng Wu , Cheng Wang , Sara Baghsorkhi , Albert Hartono
发明人： Nalini Vasudevan , Youfeng Wu , Cheng Wang , Sara Baghsorkhi , Albert Hartono
IPC分类号： G06F9/44 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30036 , G06F9/30043 , G06F9/3824 , G06F9/3834
摘要： A processor includes a decoder to decode an instruction, a scheduler to schedule the instruction, and an execution unit to execute the instruction. The instruction is to load a memory operation applicable to a quantity of addresses into an execution vector. The execution vector includes a plurality of vector positions for respective addressees. The instruction is further to evaluate, for a given address in the execution vector at a vector position, whether a cache indicates that a previous memory operation was performed at a higher vector position than the vector position of the given address. The instruction is also to determine, based on the evaluation whether the cache indicates that the previous memory operation was performed at a higher vector position than the vector position of the given address, whether the memory operation will cause a memory error.

2. 发明申请

US20150268940A1 AUTOMATIC LOOP VECTORIZATION USING HARDWARE TRANSACTIONAL MEMORY 有权
标题翻译：使用硬件交易记忆的自动环路测向
公开(公告)号：US20150268940A1
公开(公告)日：2015-09-24
申请号：US14222040
申请日：2014-03-21
申请人： Sara S. Baghsorkhi , Albert Hartono , Youfeng Wu , Nalini Vasudevan , Cheng Wang
发明人： Sara S. Baghsorkhi , Albert Hartono , Youfeng Wu , Nalini Vasudevan , Cheng Wang
IPC分类号： G06F9/45
CPC分类号： G06F8/452
摘要： Technologies for automatic loop vectorization include a computing device with an optimizing compiler. During an optimization pass, the compiler identifies a loop and generates a transactional code segment including a vectorized implementation of the loop body including one or more vector memory read instructions capable of generating an exception. The compiler also generates a non-transactional fallback code segment including a scalar implementation of the loop body that is executed in response to an exception generated within the transactional code segment. The compiler may detect whether the loop contains a memory read dependent on a condition that may be updated in a previous iteration or whether the loop contains a potential data dependence between two iterations. The compiler may generate a dynamic check for an actual data dependence and an explicit transactional abort instruction to be executed when an actual data dependence exists. Other embodiments are described and claimed.
摘要翻译：用于自动循环矢量化的技术包括具有优化编译器的计算设备。在优化传递期间，编译器识别循环并生成包括循环体的向量化实现的事务代码段，其包括能够产生异常的一个或多个向量存储器读取指令。编译器还生成非事务性回退代码段，其包括响应于在事务代码段内生成的异常被执行的循环体的标量实现。编译器可以检测循环是否包含依赖于可以在先前迭代中更新的条件的存储器读取，或者循环是否包含两次迭代之间的潜在数据依赖性。当实际数据依赖性存在时，编译器可以生成实际数据依赖性和要执行的显式事务中止指令的动态检查。描述和要求保护其他实施例。

3. 发明申请

US20160188305A1 TECHNOLOGIES FOR LOW-LEVEL COMPOSABLE HIGH PERFORMANCE COMPUTING LIBRARIES 有权
标题翻译：低水平复合高性能计算机图形技术
公开(公告)号：US20160188305A1
公开(公告)日：2016-06-30
申请号：US14583657
申请日：2014-12-27
申请人： Hongbo Rong , Peng Tu , Tatiana Shpeisman , Hai Liu , Todd A. Anderson , Youfeng Wu , Arthur N. Glew , Paul M. PetersEn , Victor W. Lee , P.G. Lowney , Arch D. Robinson , Cheng Wang
发明人： Hongbo Rong , Peng Tu , Tatiana Shpeisman , Hai Liu , Todd A. Anderson , Youfeng Wu , Arthur N. Glew , Paul M. PetersEn , Victor W. Lee , P.G. Lowney , Arch D. Robinson , Cheng Wang
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/43 , G06F8/31 , G06F8/443 , G06F8/4441 , G06F8/453 , G06F8/49 , G06F8/54
摘要： Technologies for generating composable library functions include a first computing device that includes a library compiler configured to compile a composable library and second computing device that includes an application compiler configured to compose library functions of the composable library based on a plurality of abstractions written at different levels of abstractions. For example, the abstractions may include an algorithm abstraction at a high level, a blocked-algorithm abstraction at medium level, and a region-based code abstraction at a low level. Other embodiments are described and claimed herein.
摘要翻译：用于生成可组合库函数的技术包括：第一计算设备，其包括被配置为编译可组合库的库编译器和第二计算设备，所述第二计算设备包括应用编译器，所述应用编译器被配置为基于以不同级别写入的多个抽象来组合所述可组合库的库函数的抽象。例如，抽象可以包括高级别的算法抽象，中等级别的阻塞算法抽象，以及低级别的基于区域的代码抽象。在此描述和要求保护的其它实施例。

4. 发明申请

US20140208085A1 INSTRUCTION AND LOGIC TO EFFICIENTLY MONITOR LOOP TRIP COUNT 有权
标题翻译：指令和逻辑到有效的监视器循环次数
公开(公告)号：US20140208085A1
公开(公告)日：2014-07-24
申请号：US13996861
申请日：2012-03-30
申请人： Jaewoong Chung , Hyunchul Park , Hongbo Rong , Cheng Wang , Youfeng Wu
发明人： Jaewoong Chung , Hyunchul Park , Hongbo Rong , Cheng Wang , Youfeng Wu
IPC分类号： G06F9/32
CPC分类号： G06F9/325 , G06F8/443 , G06F9/30072 , G06F9/3842 , G06F9/3857 , G06F11/3409 , G06F11/348 , G06F2201/88
摘要： Logic and instruction to efficiently monitor loop trip count. Loop trip count information of a loop may be stored in a dedicated hardware buffer. Average loop trip count of the loop may be calculated based on the stored loop trip count information. Based on the average trip count, loop optimizations may be applied or removed from the loop. The stored loop trip count information may include an identifier identifying the loop, a total loop trip count of the loop, and an exit count of the loop.
摘要翻译：有效监控回路行程数的逻辑和指令。循环的循环行程计数信息可以存储在专用硬件缓冲器中。可以基于存储的循环行程计数信息来计算循环的平均循环行程计数。基于平均行程计数，循环优化可以从循环中应用或移除。存储的循环行程计数信息可以包括标识循环的标识符，循环的总循环行程计数以及循环的退出计数。

5. 发明授权

US08443343B2 Context-sensitive slicing for dynamically parallelizing binary programs 有权
标题翻译：用于动态并行化二进制程序的上下文相关切片
公开(公告)号：US08443343B2
公开(公告)日：2013-05-14
申请号：US12607589
申请日：2009-10-28
申请人： Joseph Blomstedt , Cheng Wang , Youfeng Wu
发明人： Joseph Blomstedt , Cheng Wang , Youfeng Wu
IPC分类号： G06F9/45
CPC分类号： G06F11/3604 , G06F8/433 , G06F8/456
摘要： In one embodiment of the invention a method comprising (1) receiving an unstructured binary code region that is single-threaded; (2) determining a slice criterion for the region; (3) determining a call edge, a return edge, and a fallthrough pseudo-edge for the region based on analysis of the region at a binary level; and (4) determining a context-sensitive slice based on the call edge, the return edge, the fallthrough pseudo-edge, and the slice criterion. Embodiments of the invention may include a program analysis technique that can be used to provide context-sensitive slicing of binary programs for slicing hot regions identified at runtime, with few underlying assumptions about the program from which the binary is derived. Also, in an embodiment a slicing method may include determining a context-insensitive slice, when a time limit is met, by determining the context-insensitive slice while treating call edges as a normal control flow edges.
摘要翻译：在本发明的一个实施例中，一种方法包括（1）接收单线程的非结构化二进制码区域; （2）确定该区域的切片标准; （3）基于二进制级别的区域的分析确定该区域的通话边缘，返回边缘和下降伪边缘; 和（4）基于呼叫边缘，返回边缘，下降伪边缘和切片标准来确定上下文敏感切片。本发明的实施例可以包括程序分析技术，其可以用于提供二进制程序的上下文敏感切片，用于对在运行时识别的热区域进行切片，而关于从其导出二进制的程序的几个基本假设。此外，在一个实施例中，切片方法可以包括当满足时间限制时，通过在将呼叫边缘视为正常控制流边缘的同时确定上下文不敏感切片来确定上下文不敏感切片。

6. 发明申请

US20120198426A1 METHODS AND APPARATUS TO FORM A RESILIENT OBJECTIVE INSTRUCTION CONSTRUCT 有权
标题翻译：形成适应性目标指导建议的方法和设备
公开(公告)号：US20120198426A1
公开(公告)日：2012-08-02
申请号：US13442703
申请日：2012-04-09
申请人： Youfeng Wu , Cheng Wang , Ho-Seop Kim
发明人： Youfeng Wu , Cheng Wang , Ho-Seop Kim
IPC分类号： G06F9/45
CPC分类号： G06F11/28 , G06F8/52 , G06F9/30087 , G06F9/45516
摘要： Methods and an apparatus to form a resilient objective instruction construct are provided. An example method obtains a source instruction construct and forms a resilient objective instruction construct by compiling one or more resilient transactions.
摘要翻译：提供了形成弹性目标指令结构的方法和装置。示例性方法通过编译一个或多个弹性事务来获得源指令结构并形成弹性目标指令结构。

7. 发明授权

US08060482B2 Efficient and consistent software transactional memory 有权
标题翻译：高效一致的软件事务内存
公开(公告)号：US08060482B2
公开(公告)日：2011-11-15
申请号：US11648012
申请日：2006-12-28
申请人： Cheng Wang , Youfeng Wu , Wei-Yu Chen , Bratin Saha , Ali-Reza Adl-Tabatabai
发明人： Cheng Wang , Youfeng Wu , Wei-Yu Chen , Bratin Saha , Ali-Reza Adl-Tabatabai
IPC分类号： G06F7/00 , G06F17/00 , G06F17/30
CPC分类号： G06F8/458 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/3863 , G06F9/467
摘要： A method and apparatus for efficient and consistent validation/conflict detection in a Software Transactional Memory (STM) system is herein described. A version check barrier is inserted after a load to compare versions of loaded values before and after the load. In addition, a global timestamp (GTS) is utilized to track a latest committed transaction. Each transaction is associated with a local timestamp (LTS) initialized to the GTS value at the start of a transaction. As a transaction commits it updates the GTS to a new value and sets versions of modified locations to the new value. Pending transactions compare versions determined in read barriers to their LTS. If the version is greater than their LTS indicating another transaction has committed after the pending transaction started and initialized the LTS, then the pending transaction validates its read set to maintain efficient and consistent transactional execution.
摘要翻译：这里描述了用于在软件事务存储器（STM）系统中有效且一致的验证/冲突检测的方法和装置。在加载之后插入版本检查障碍，以便在加载之前和之后比较加载值的版本。此外，使用全局时间戳（GTS）来跟踪最近提交的事务。每个事务与在事务开始时初始化为GTS值的本地时间戳（LTS）相关联。作为事务提交，将GTS更新为新值，并将修改的位置的版本设置为新值。待处理的交易将比较其在LTS阅读障碍中确定的版本。如果版本大于其LTS，指示在挂起事务启动并初始化LTS之后另一个事务已经提交，则挂起的事务会验证其读取集合以保持有效且一致的事务执行。

8. 发明授权

US07937620B2 Transient fault detection by integrating an SRMT code and a non SRMT code in a single application 有权
公开(公告)号：US07937620B2
公开(公告)日：2011-05-03
申请号：US11745403
申请日：2007-05-07
申请人： Cheng Wang , Youfeng Wu
发明人： Cheng Wang , Youfeng Wu
IPC分类号： G06F11/00 , G06F11/14
CPC分类号： G06F11/1497 , G06F8/457
摘要： Disclosed is a method for running a first code generated by a Software-based Redundant Multi-Threading (SRMT) compiler along with a second code generated by a normal compiler at runtime, the first code including a first function and a second function, the second code including a third function. The method comprises running the first function in a leading thread and a tailing thread (104); running the third function in a single thread (106), the leading thread calls the third function and running the second function in the leading thread and the tailing thread (108), the third function calls the second function. The present disclosure provides a mechanism for handling function calls wherein SRMT functions and binary functions can call each other irrespective of whether the callee function is a SRMT function or a binary function and thereby dynamically adjusts reliability and performance tradeoff based on run-time information and user selectable policies.

9. 发明授权

US07844946B2 Methods and apparatus to form a transactional objective instruction construct from lock-based critical sections 有权
标题翻译：从基于锁的关键部分形成事务性目标指令构造的方法和装置
公开(公告)号：US07844946B2
公开(公告)日：2010-11-30
申请号：US11535205
申请日：2006-09-26
申请人： Youfeng Wu , Cheng Wang
发明人： Youfeng Wu , Cheng Wang
IPC分类号： G06F9/44 , G06F9/46
CPC分类号： G06F9/466 , G06F9/524
摘要： Methods and an apparatus for forming a transaction object instruction construct are provided. An example method translates a source instruction construct to form a transactional objective instruction construct, executes the transactional objective instruction construct, intercepts an aborted transaction associated with the transactional objective instruction construct during execution, maintains a graph of nodes and edges associated with the executed transactional objective instruction construct to predict a deadlock situation, and resolves the deadlock situation associated with the transactional objective instruction construct based on the graph.
摘要翻译：提供了用于形成交易对象指令结构的方法和装置。一个示例性方法将源指令结构转换成一个事务性目标指令结构，执行事务目标指令结构，在执行期间拦截与事务性目标指令结构相关联的异常事务，维护与执行的事务目标相关联的节点和边的图指令结构来预测死锁情况，并根据图表解决与事务性目标指令构造相关的死锁情况。

10. 发明授权

US07694281B2 Two-pass MRET trace selection for dynamic optimization 有权
标题翻译：双向MRET跟踪选择用于动态优化
公开(公告)号：US07694281B2
公开(公告)日：2010-04-06
申请号：US11241527
申请日：2005-09-30
申请人： Cheng Wang , Bixia Zheng , Ho-seop Kim , Mauricio Breternitz, Jr. , Youfeng Wu
发明人： Cheng Wang , Bixia Zheng , Ho-seop Kim , Mauricio Breternitz, Jr. , Youfeng Wu
IPC分类号： G06F9/44
CPC分类号： G06F9/45516
摘要： A first potential hot trace of a program is determined. A second potential hot trace of the program is determined. A common path from the first potential hot trace and the second potential hot trace is selected as the selected hot trace of the program.
摘要翻译：确定程序的第一个潜在的热迹。确定程序的第二个潜在的热迹。选择第一个潜在热痕迹和第二个潜在热痕迹的常见路径作为程序的选定热痕迹。

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